/* $NoKeywords:$ */ /** * @file * * AMD CPU Cache Flush On Halt Function for Family 15h Trinity. * * Contains code to initialize Cache Flush On Halt feature for Family 15h Trinity. * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: CPU/Family/0x15/TN * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ * */ /* ****************************************************************************** * * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. * * AMD is granting you permission to use this software (the Materials) * pursuant to the terms and conditions of your Software License Agreement * with AMD. This header does *NOT* give you permission to use the Materials * or any rights under AMD's intellectual property. Your use of any portion * of these Materials shall constitute your acceptance of those terms and * conditions. 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Use of the Materials by the * Government constitutes acknowledgement of AMD's proprietary rights in them. * * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any * direct product thereof will be exported directly or indirectly, into any * country prohibited by the United States Export Administration Act and the * regulations thereunder, without the required authorization from the U.S. * government nor will be used for any purpose prohibited by the same. ****************************************************************************** *---------------------------------------------------------------------------- */ /* *---------------------------------------------------------------------------- * MODULES USED * *---------------------------------------------------------------------------- */ #include "AGESA.h" #include "amdlib.h" #include "cpuRegisters.h" #include "cpuServices.h" #include "cpuFamilyTranslation.h" #include "cpuPostInit.h" #include "cpuF15PowerMgmt.h" #include "cpuF15TnPowerMgmt.h" #include "cpuFeatures.h" #include "Filecode.h" CODE_GROUP (G3_DXE) RDATA_GROUP (G3_DXE) #define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS * *---------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------- * TYPEDEFS AND STRUCTURES * *---------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------- * PROTOTYPES OF LOCAL FUNCTIONS * *---------------------------------------------------------------------------- */ VOID SetF15TnCacheFlushOnHaltRegister ( IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, IN UINT64 EntryPoint, IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ); /*---------------------------------------------------------------------------------------- * P U B L I C F U N C T I O N S *---------------------------------------------------------------------------------------- */ /* -----------------------------------------------------------------------------*/ /** * Enable Cpu Cache Flush On Halt Function * * @param[in] FamilySpecificServices The current Family Specific Services. * @param[in] EntryPoint Timepoint designator. * @param[in] PlatformConfig Contains the runtime modifiable feature input data. * @param[in] StdHeader Config Handle for library, services. */ VOID SetF15TnCacheFlushOnHaltRegister ( IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, IN UINT64 EntryPoint, IN PLATFORM_CONFIGURATION *PlatformConfig, IN AMD_CONFIG_PARAMS *StdHeader ) { PCI_ADDR PciAddress; CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2; CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1; CSTATE_CTRL1_REGISTER CstateCtrl1; if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { // Set D18F3xDC[CacheFlushOnHaltCtl] != 0 // Set D18F3xDC[CacheFlushOnHaltTmr] PciAddress.AddressValue = CPTC2_PCI_ADDR; LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); ClkPwrTimingCtrl2.CacheFlushOnHaltCtl = 7; ClkPwrTimingCtrl2.CacheFlushOnHaltTmr = 0x14; LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // Set D18F4x128[CacheFlushTmr, CacheFlushSucMonThreshold] PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR; LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); CstatePolicyCtrl1.CacheFlushTmr = 0x14; CstatePolicyCtrl1.CacheFlushSucMonThreshold = 7; LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); // Set cache flush bits in D18F4x118 PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR; LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); // Set C-state Action Field 0 CstateCtrl1.CacheFlushEnCstAct0 = 1; CstateCtrl1.CacheFlushTmrSelCstAct0 = 2; CstateCtrl1.ClkDivisorCstAct0 = 0; // Set C-state Action Field 1 CstateCtrl1.CacheFlushEnCstAct1 = 1; CstateCtrl1.CacheFlushTmrSelCstAct1 = 1; CstateCtrl1.ClkDivisorCstAct1 = 0; LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); //Override the default setting IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader); } } CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt = { 0, SetF15TnCacheFlushOnHaltRegister };