/* $NoKeywords:$ */ /** * @file * * Create outline and references for GNB Component mainpage documentation. * * Design guides, maintenance guides, and general documentation, are * collected using this file onto the documentation mainpage. * This file contains doxygen comment blocks, only. * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: Documentation * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ * */ /* ***************************************************************************** * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Advanced Micro Devices, Inc. nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * *************************************************************************** * */ /** * @page F12PcieLaneDescription Family 0x12 PCIe/DDI Lanes *
Lane ID | Lane group | Pin |
0 | SB | P_SB_RX[P/N]/TX[P/N][0] |
1 | SB | P_SB_RX[P/N]/TX[P/N][1] |
2 | SB | P_SB_RX[P/N]/TX[P/N][2] |
3 | SB | P_SB_RX[P/N]/TX[P/N][3] |
4 | GPP | P_GPP_RX[P/N]/TX[P/N][0] |
5 | GPP | P_GPP_RX[P/N]/TX[P/N][1] |
6 | GPP | P_GPP_RX[P/N]/TX[P/N][2] |
7 | GPP | P_GPP_RX[P/N]/TX[P/N][3] |
8 | GFX | P_GFX_RX[P/N]/TX[P/N][0] |
9 | GFX | P_GFX_RX[P/N]/TX[P/N][1] |
10 | GFX | P_GFX_RX[P/N]/TX[P/N][2] |
11 | GFX | P_GFX_RX[P/N]/TX[P/N][3] |
12 | GFX | P_GFX_RX[P/N]/TX[P/N][4] |
13 | GFX | P_GFX_RX[P/N]/TX[P/N][5] |
14 | GFX | P_GFX_RX[P/N]/TX[P/N][6] |
15 | GFX | P_GFX_RX[P/N]/TX[P/N][7] |
16 | GFX | P_GFX_RX[P/N]/TX[P/N][8] |
17 | GFX | P_GFX_RX[P/N]/TX[P/N][9] |
18 | GFX | P_GFX_RX[P/N]/TX[P/N][10] |
19 | GFX | P_GFX_RX[P/N]/TX[P/N][11] |
20 | GFX | P_GFX_RX[P/N]/TX[P/N][12] |
21 | GFX | P_GFX_RX[P/N]/TX[P/N][13] |
22 | GFX | P_GFX_RX[P/N]/TX[P/N][14] |
23 | GFX | P_GFX_RX[P/N]/TX[P/N][15] |
24 | DDI | DP1_TXP/N[0] |
25 | DDI | DP1_TXP/N[1] |
26 | DDI | DP1_TXP/N[2] |
27 | DDI | DP1_TXP/N[3] |
28 | DDI | DP0_TXP/N[0] |
29 | DDI | DP0_TXP/N[1] |
30 | DDI | DP0_TXP/N[2] |
31 | DDI | DP0_TXP/N[3] |
Lane ID | Lane group | Pin |
0 | SB | P_SB_RX[P/N]/TX[P/N][0] |
1 | SB | P_SB_RX[P/N]/TX[P/N][1] |
2 | SB | P_SB_RX[P/N]/TX[P/N][2] |
3 | SB | P_SB_RX[P/N]/TX[P/N][3] |
4 | GPP | P_GPP_RX[P/N]/TX[P/N][0] |
5 | GPP | P_GPP_RX[P/N]/TX[P/N][1] |
6 | GPP | P_GPP_RX[P/N]/TX[P/N][2] |
7 | GPP | P_GPP_RX[P/N]/TX[P/N][3] |
8 | DDI | DP0_TXP/N[0] |
9 | DDI | DP0_TXP/N[1] |
10 | DDI | DP0_TXP/N[2] |
11 | DDI | DP0_TXP/N[3] |
12 | DDI | DP1_TXP/N[0] |
13 | DDI | DP1_TXP/N[1] |
14 | DDI | DP1_TXP/N[2] |
15 | DDI | DP1_TXP/N[3] |
PCIe port configurations *for lanes 8 through 23.
* *
* Configuration * |
*
* PCIe Port Device Number * |
*
* Start Lane (Start Lane in reverse * configuration) * |
*
* End Line (End lane in reverse * configuration) * |
*
* Config A * |
*
* 2 * |
*
* 8(23) * |
*
* 23(8) * |
*
* Config B * |
*
* 2 * |
*
* 8(15) * |
*
* 15(8) * |
*
* 8(11) * |
*
* 11(8) * |
* ||
* 8(9) * |
*
* 9(8) * |
* ||
* 10(11) * |
*
* 11(10) * |
* ||
* 12(15) * |
*
* 15(12) * |
* ||
* 12(13) * |
*
* 13(12) * |
* ||
* 14(15) * |
*
* 15(14) * |
* ||
* 3 * |
*
* 16(23) * |
*
* 23(16) * |
* |
* 16(19) * |
*
* 19(16) * |
* ||
* 16(17) * |
*
* 17(16) * |
* ||
* 18(19) * |
*
* 19(18) * |
* ||
* 20(23) * |
*
* 23(20) * |
* ||
* 20(21) * |
*
* 21(20) * |
* ||
* 22(23) * |
*
* 23(22) * |
*
* *
PCIe port configurations *for lanes 4 through 7.
* *
* Configuration * |
*
* PCIe Port Device Number * |
*
* Start Lane (Start Lane in reverse * configuration) * |
*
* End Line (End lane in reverse * configuration) * |
*
* Config A * |
*
* 4 * |
*
* 4(7) * |
*
* 7(4) * |
*
* * |
*
* * |
* ||
* Config B * |
*
* 4 * |
*
* 4(5) * |
*
* 5(4) * |
*
* 4 * |
*
* 4 * |
* ||
* 5 * |
*
* 5 * |
* ||
* 5 * |
*
* 6(7) * |
*
* 7(6) * |
* |
* 6 * |
*
* 6 * |
* ||
* 7 * |
*
* 7 * |
* ||
* Config C * |
*
* 4 * |
*
* 4(5) * |
*
* 5(4) * |
*
* 4 * |
*
* 4 * |
* ||
* 5 * |
*
* 5 * |
* ||
* 5 * |
*
* 6 * |
*
* 6 * |
* |
* 6 * |
*
* 7 * |
*
* 7 * |
* |
* Config D * |
*
* 4 * |
*
* 4 * |
*
* 4 * |
*
* 5 * |
*
* 5 * |
*
* 5 * |
* |
* 6 * |
*
* 6 * |
*
* 6 * |
* |
* 7 * |
*
* 7 * |
*
* 7 * |
*
*
* *
DDI link configurations *for lanes 24 through 31.
* *
* Configuration * |
*
* Connector type * |
*
* Start Lane (Start Lane in reverse * configuration) * |
*
* End Line (End lane in reverse * configuration) * |
*
* Config A * |
*
* Dual Link DVI-D * |
*
* 24(31) * |
*
* 31(24) * |
*
* Config B * |
*
* HDMI *Single Link DVI-D *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 24 * |
*
* 27 * |
*
* HDMI *Single Link DVI-D *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 28 * |
*
* 31 * |
*
* *
DDI link configurations *for lanes 8 through 23.
* *
* Configuration * |
*
* Connector type * |
*
* Start Lane (Start Lane in reverse * configuration) * |
*
* End Line (End lane in reverse * configuration) * |
*
* Config A * |
*
* Dual Link DVI-D * |
*
* 24(31) * |
*
* 31(24) * |
*
* Config B * |
*
* Dual Link DVI-D * |
*
* 8(15) * |
*
* 15(8) * |
*
* Dual Link DVI-D * |
*
* 16(23) * |
*
* 23(16) * |
* |
* Config C * |
*
* Dual Link DVI-D * |
*
* 8(15) * |
*
* 15(8) * |
*
* HDMI *Single Link DVI-D *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 16 * |
*
* 19 * |
* |
* HDMI *Single Link DVI-D *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 20 * |
*
* 23 * |
* |
* Config D * |
*
* HDMI *Single Link DVI-D *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 8 * |
*
* 11 * |
*
* HDMI *Single Link DVI-D *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 12 * |
*
* 15 * |
* |
* Dual Link DVI-D * |
*
* 16(23) * |
*
* 23(16) * |
* |
* Config E * |
*
* HDMI *Single Link DVI-D *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 8 * |
*
* 11 * |
*
* HDMI *Single Link DVI-D *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 12 * |
*
* 15 * |
* |
* HDMI *Single Link DVI-D *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 16 * |
*
* 19 * |
* |
* HDMI *Single Link DVI-D *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 20 * |
*
* 23 * |
*
PCIe port *configurations for lanes 4 through 7.
* *
* Configuration * |
*
* PCIe Port Device Number * |
*
* Start Lane (Start Lane in reverse * configuration) * |
*
* End Line (End lane in reverse * configuration) * |
*
* Config A * |
*
* 4 * |
*
* 4(7) * |
*
* 7(4) * |
*
* * |
*
* * |
* ||
* Config B * |
*
* 4 * |
*
* 4(5) * |
*
* 5(4) * |
*
* 4 * |
*
* 4 * |
* ||
* 5 * |
*
* 5 * |
* ||
* 5 * |
*
* 6(7) * |
*
* 7(6) * |
* |
* 6 * |
*
* 6 * |
* ||
* 7 * |
*
* 7 * |
* ||
* Config C * |
*
* 4 * |
*
* 4(5) * |
*
* 5(4) * |
*
* 4 * |
*
* 4 * |
* ||
* 5 * |
*
* 5 * |
* ||
* 5 * |
*
* 6 * |
*
* 6 * |
* |
* 6 * |
*
* 7 * |
*
* 7 * |
* |
* Config D * |
*
* 4 * |
*
* 4 * |
*
* 4 * |
*
* 5 * |
*
* 5 * |
*
* 5 * |
* |
* 6 * |
*
* 6 * |
*
* 6 * |
* |
* 7 * |
*
* 7 * |
*
* 7 * |
*
*
* *
CRT/DDI link *configurations for lanes 8 through 19.
* *
* Configuration * |
*
* Connector type * |
*
* Start Lane (Start Lane in reverse * configuration) * |
*
* End Line (End lane in reverse * configuration) * |
*
* Config A * |
*
* HDMI *Single Link DVI-D *Single Link DVI-I* *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 8 * |
*
* 11 * |
*
* HDMI *Single Link DVI-D *Single Link DVI-I* *DP *eDP *Travis DP-to-CRT *Travis DP-to-LVDS *Hudson2 DP-to-CRT * |
*
* 12 * |
*
* 15 * |
* |
* CRT* * |
*
* 16 * |
*
* 19 * |
* |
* * - Only one connector of this type can exist in overall configuration * |
*