/* * This file is part of the coreboot project. * * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com> * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H #define SUPERIO_ASPEED_COMMON_ROMSTAGE_H #include <arch/io.h> #include <device/pnp_type.h> #include <stdint.h> void aspeed_enable_serial(pnp_devfn_t dev, uint16_t iobase); void pnp_enter_conf_state(pnp_devfn_t dev); void pnp_exit_conf_state(pnp_devfn_t dev); #endif /* SUPERIO_ASPEED_COMMON_ROMSTAGE_H */