##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##

config SOUTHBRIDGE_INTEL_LYNXPOINT
	bool

if SOUTHBRIDGE_INTEL_LYNXPOINT

config SOUTH_BRIDGE_OPTIONS # dummy
	def_bool y
	select SOUTHBRIDGE_INTEL_COMMON
	select IOAPIC
	select HAVE_HARD_RESET
	select HAVE_USBDEBUG_OPTIONS
	select USE_WATCHDOG_ON_BOOT
	select PCIEXP_ASPM
	select PCIEXP_COMMON_CLOCK
	select SPI_FLASH

config INTEL_LYNXPOINT_LP
	bool
	default n
	help
	  Set this option to y for Lynxpont LP (Haswell ULT).

config EHCI_BAR
	hex
	default 0xe8000000

config BOOTBLOCK_SOUTHBRIDGE_INIT
	string
	default "southbridge/intel/lynxpoint/bootblock.c"

config SERIRQ_CONTINUOUS_MODE
	bool
	default n
	help
	  If you set this option to y, the serial IRQ machine will be
	  operated in continuous mode.

config HAVE_IFD_BIN
	bool
	default y

config BUILD_WITH_FAKE_IFD
	bool "Build with a fake IFD"
	default y if !HAVE_IFD_BIN
	help
	  If you don't have an Intel Firmware Descriptor (ifd.bin) for your
	  board, you can select this option and coreboot will build without it.
	  Though, the resulting coreboot.rom will not contain all parts required
	  to get coreboot running on your board. You can however write only the
	  BIOS section to your board's flash ROM and keep the other sections
	  untouched. Unfortunately the current version of flashrom doesn't
	  support this yet. But there is a patch pending [1].

	  WARNING: Never write a complete coreboot.rom to your flash ROM if it
		   was built with a fake IFD. It just won't work.

          [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html

config IFD_BIOS_SECTION
	depends on BUILD_WITH_FAKE_IFD
	string
	default ""

config IFD_ME_SECTION
	depends on BUILD_WITH_FAKE_IFD
	string
	default ""

config IFD_GBE_SECTION
	depends on BUILD_WITH_FAKE_IFD
	string
	default ""

config IFD_PLATFORM_SECTION
	depends on BUILD_WITH_FAKE_IFD
	string
	default ""

config IFD_BIN_PATH
	string "Path to intel firmware descriptor"
	depends on !BUILD_WITH_FAKE_IFD
	default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"

config HAVE_ME_BIN
	bool "Add Intel Management Engine firmware"
	default y
	help
	  The Intel processor in the selected system requires a special firmware
	  for an integrated controller called Management Engine (ME). The ME
	  firmware might be provided in coreboot's 3rdparty repository. If
	  not and if you don't have the firmware elsewhere, you can still
	  build coreboot without it. In this case however, you'll have to make
	  sure that you don't overwrite your ME firmware on your flash ROM.

config ME_BIN_PATH
	string "Path to management engine firmware"
	depends on HAVE_ME_BIN
	default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"

config IFD_BIN_PATH
	string "Path to intel firmware descriptor"
	default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"

config ME_MBP_CLEAR_LATE
	bool "Defer wait for ME MBP Cleared"
	default y
	help
	  If you set this option to y, the Management Engine driver
	  will defer waiting for the MBP Cleared indicator until the
	  finalize step.  This can speed up boot time if the ME takes
	  a long time to indicate this status.

config FINALIZE_USB_ROUTE_XHCI
	bool "Route all ports to XHCI controller in finalize step"
	default y
	help
	  If you set this option to y, the USB ports will be routed
	  to the XHCI controller during the finalize SMM callback.

endif