/* SPDX-License-Identifier: GPL-2.0-only */ #include <types.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <soc/nvs.h> #include <southbridge/intel/common/pmutil.h> #include "i82801gx.h" /* I945 */ #define SMRAM 0x9d #define D_OPEN (1 << 6) #define D_CLS (1 << 5) #define D_LCK (1 << 4) #define G_SMRANE (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) /* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; u32 data, mask = 0; int i; trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR trap_cycle = RCBA32(0x1e10); for (i = 16; i < 20; i++) { if (trap_cycle & (1 << i)) mask |= (0xff << ((i - 16) << 3)); } /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { if (gnvs && gnvs->smif) io_trap_handler(gnvs->smif); // call function smif return; } /* IOTRAP(2) currently unused * IOTRAP(1) currently unused */ /* IOTRAP(0) SMIC: currently unused */ printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); for (i = 0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ data = RCBA32(0x1e18); printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); } #undef IOTRAP } void southbridge_finalize_all(void) { }