config SOC_NVIDIA_TEGRA124 select ARCH_BOOTBLOCK_ARMV4 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select DYNAMIC_CBMEM select ARM_BOOTBLOCK_CUSTOM bool default n if SOC_NVIDIA_TEGRA124 config BOOTBLOCK_CPU_INIT string default "soc/nvidia/tegra124/bootblock.c" help CPU/SoC-specific bootblock code. This is useful if the bootblock must load microcode or copy data from ROM before searching for the bootblock. # ROM image layout. # # 0x00000 Combined bootblock and BCT blob # 0x18000 Master CBFS header. # 0x18080 Free for CBFS data. # # iRAM (256k) layout. # 0x4000_0000 BootROM runtime data/stack area, can be reclaimed after BootROM. # +0000 (BootROM) Boot Information Table. # +0100 (BootROM) BCT. # --------------------------------------------------------------------- # +0000 (Coreboot) TTB 16KB. # +4000 (Coreboot) Stack. # 0x4000_E000 Valid for anything to be executed after BootROM (effective entry # point address specified in BCT). # +0000 (Coreboot) Bootblock (max 36k). # +9000 (Coreboot) ROM stage (max 36k). # 0x4002_0000 (Coreboot) Cache of CBFS. # 0x4003_FFFF End of iRAM. config BOOTBLOCK_ROM_OFFSET hex default 0x0 config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" default 0x18000 config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" default 0x18080 config SYS_SDRAM_BASE hex default 0x80000000 config BOOTBLOCK_BASE hex default 0x4000e000 config ROMSTAGE_BASE hex default 0x40017000 config RAMSTAGE_BASE hex default 0x80200000 config STACK_TOP hex default 0x4000c000 config STACK_BOTTOM hex default 0x40004000 config STACK_SIZE hex default 0x800 # TTB needs to be aligned to 16KB. Stick it in iRAM. config TTB_BUFFER hex "memory address of the TTB buffer" default 0x40000000 config CBFS_CACHE_ADDRESS hex "memory address to put CBFS cache data" default 0x40020000 config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00020000 endif