## SPDX-License-Identifier: GPL-2.0-only

config SOC_INTEL_COOPERLAKE_SP
	bool
	select XEON_SP_COMMON_BASE
	select PLATFORM_USES_FSP2_2
	select CACHE_MRC_SETTINGS
	select NO_FSP_TEMP_RAM_EXIT
	select HAVE_INTEL_FSP_REPO
	select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
	select UDK_202005_BINDING
	help
	  Intel Cooper Lake-SP support

if SOC_INTEL_COOPERLAKE_SP

config FSP_HEADER_PATH
	default "3rdparty/fsp/CedarIslandFspBinPkg/Include"

config FSP_FD_PATH
	default "3rdparty/fsp/CedarIslandFspBinPkg/Fsp.fd"

config MAX_SOCKET
	int
	default 2

config MAX_CPUS
	int
	default 255

config PCR_BASE_ADDRESS
	hex
	default 0xfd000000
	help
	  This option allows you to select MMIO Base Address of sideband bus.

config DCACHE_RAM_BASE
	hex
	default 0xfe800000

config DCACHE_RAM_SIZE
	hex
	default 0x1fff00
	help
	  The size of the cache-as-ram region required during bootblock
	  and/or romstage. FSP-T reserves the upper 0x100 for
	  FspReservedBuffer.

config DCACHE_BSP_STACK_SIZE
	hex
	default 0x40000
	help
	  The amount of anticipated stack usage in CAR by bootblock and
	  other stages. It needs to include FSP-M stack requirement and
	  CB romstage stack requirement. The integration documentation
	  says this needs to be 256KiB.

config FSP_M_RC_HEAP_SIZE
	hex
	default 0x130000
	help
	  On xeon_sp/cpx FSP-M has two separate heap managers, one regular
	  whose size and base are controllable via the StackBase and
	  StackSize UPDs and a 'rc' heap manager that is statically
	  allocated at 0xfe800000 (the CAR base) and consumes about 0x130000
	  bytes of memory.

config CPU_MICROCODE_CBFS_LOC
	hex
	default 0xfff0fdc0

config CPU_MICROCODE_CBFS_LEN
	hex
	default 0x7C00

config STACK_SIZE
	hex
	default 0x4000

config FSP_TEMP_RAM_SIZE
	hex
	depends on FSP_USES_CB_STACK
	default 0x40000
	help
	  The amount of anticipated heap usage in CAR by FSP.
	  Refer to Platform FSP integration guide document to know
	  the exact FSP requirement for Heap setup.  The FSP integration
	  documentation says this needs to be at least 128KiB, but practice
	  show this needs to be 256KiB or more.

config IED_REGION_SIZE
	hex
	default 0x400000

config IFD_CHIPSET
	string
	default "lbg"

config SOC_INTEL_COMMON_BLOCK_P2SB
	def_bool y

config CPU_BCLK_MHZ
	int
	default 100

# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
# Default value is set to one socket, full config.
config DIMM_MAX
	default 12

# DDR4
config DIMM_SPD_SIZE
	default 512

config XEON_SP_HAVE_IIO_IOAPIC
	bool
	default y

if INTEL_TXT

config INTEL_TXT_SINIT_SIZE
	hex
	default 0x50000
	help
	  According to document number 572782 this needs to be 256KiB
	  for the SINIT module and 64KiB for SINIT data.

config INTEL_TXT_HEAP_SIZE
	hex
	default 0xf0000
	help
	  This must be 960KiB according to 572782.

endif # INTEL_TXT

endif