/* SPDX-License-Identifier: GPL-2.0-only */ /* * This file is created based on Intel Tiger Lake Processor PCH Datasheet * Document number: 575857 * Chapter number: 4, 29 */ #include <bootstate.h> #include <commonlib/console/post_codes.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <device/mmio.h> #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <intelpch/lockdown.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/pm.h> #include <soc/smbus.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> #include <spi-generic.h> static void pch_finalize(void) { /* TCO Lock down */ tco_lockdown(); /* TODO: Add Thermal Configuration */ /* * Disable ACPI PM timer based on dt policy * * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO */ if (!CONFIG(USE_PM_ACPI_TIMER)) pmc_disable_acpi_timer(); pmc_clear_pmcon_sts(); } static void tbt_finalize(void) { int i; const struct device *dev; /* Disable Thunderbolt PCIe root ports bus master */ for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); if (dev) pci_dev_disable_bus_master(dev); } } static void sa_finalize(void) { if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) sa_lock_pam(); } static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); apm_control(APM_CNT_FINALIZE); tbt_finalize(); sa_finalize(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);