config SOC_INTEL_TIGERLAKE bool help Intel Tigerlake support config SOC_INTEL_TIGERLAKE_PCH_H bool if SOC_INTEL_TIGERLAKE config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_INTEL_TME select CPU_SUPPORTS_PM_TIMER_EMULATION select DRIVERS_USB_ACPI select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select GENERIC_GPIO_LIB select HAVE_FSP_GOP select HAVE_INTEL_FSP_REPO select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED select SF_MASK_2WAYS_PER_BIT if INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select MP_SERVICES_PPI_V1 select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_2 select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_CSE_SET_EOP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM config MAX_CPUS int default 16 if SOC_INTEL_TIGERLAKE_PCH_H default 8 config DCACHE_RAM_BASE default 0xfef00000 config DCACHE_RAM_SIZE default 0x80000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex default 0x40400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE hex default 0x20000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. config CHIPSET_DEVICETREE string default "soc/intel/tigerlake/chipset_pch_h.cb" if SOC_INTEL_TIGERLAKE_PCH_H default "soc/intel/tigerlake/chipset.cb" config EXT_BIOS_WIN_BASE default 0xf8000000 config EXT_BIOS_WIN_SIZE default 0x2000000 config IFD_CHIPSET string default "tgl" config IED_REGION_SIZE hex default 0x400000 config HEAP_SIZE hex default 0x10000 config MAX_ROOT_PORTS int default 24 if SOC_INTEL_TIGERLAKE_PCH_H default 12 config MAX_PCIE_CLOCK_SRC int default 16 if SOC_INTEL_TIGERLAKE_PCH_H default 7 config SMM_TSEG_SIZE hex default 0x800000 config SMM_RESERVED_SIZE hex default 0x200000 config PCR_BASE_ADDRESS hex default 0xfd000000 help This option allows you to select MMIO Base Address of sideband bus. config MMCONF_BASE_ADDRESS default 0xc0000000 config CPU_BCLK_MHZ int default 100 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 config CPU_XTAL_HZ default 38400000 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 4 config SOC_INTEL_I2C_DEV_MAX int default 6 config SOC_INTEL_UART_DEV_MAX int default 3 config CONSOLE_UART_BASE_ADDRESS hex default 0xfe03e000 depends on INTEL_LPSS_UART_FOR_CONSOLE # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clcok * M) /(N *16) # TGL UART source clock: 120MHz config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex default 0x25a config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL hex default 0x7fff # Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection # in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. config TPM_CR50 select CR50_USE_LONG_INTERRUPT_PULSES config VBT_DATA_SIZE_KB int default 9 config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH config CBFS_SIZE default 0x200000 config FSP_TYPE_IOT bool default n help This option allows to select FSP IOT type from 3rdparty/fsp repo config FSP_TYPE_CLIENT bool default !FSP_TYPE_IOT help This option allows to select FSP CLIENT type from 3rdparty/fsp repo config FSP_HEADER_PATH default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Include/" if FSP_TYPE_IOT default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Include/" if FSP_TYPE_CLIENT config FSP_FD_PATH default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Fsp.fd" if FSP_TYPE_IOT default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Fsp.fd" if FSP_TYPE_CLIENT config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT int "Debug Consent for TGL" # USB DBC is more common for developers so make this default to 3 if # SOC_INTEL_DEBUG_CONSENT=y default 3 if SOC_INTEL_DEBUG_CONSENT default 0 help This is to control debug interface on SOC. Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details. Desired platform debug type are 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x2000 config DATA_BUS_WIDTH int default 128 config DIMMS_PER_CHANNEL int default 2 config MRC_CHANNEL_WIDTH int default 16 config SOC_INTEL_CRASHLOG def_bool n select SOC_INTEL_COMMON_BLOCK_CRASHLOG select ACPI_BERT help Enables CrashLog. # Intel recommends reserving the following resources per USB4 root port, # from TGL BIOS Spec (doc #611569) Revision 0.7.6 Section 7.2.5.1.5 # - 42 buses # - 194 MiB Non-prefetchable memory # - 448 MiB Prefetchable memory if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config PCIEXP_HOTPLUG_BUSES default 42 config PCIEXP_HOTPLUG_MEM default 0xc200000 # 194 MiB config PCIEXP_HOTPLUG_PREFETCH_MEM default 0x1c000000 # 448 MiB endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config INTEL_GMA_BCLV_OFFSET default 0xc8258 config INTEL_GMA_BCLV_WIDTH default 32 config INTEL_GMA_BCLM_OFFSET default 0xc8254 config INTEL_GMA_BCLM_WIDTH default 32 endif