## SPDX-License-Identifier: GPL-2.0-only

config SOC_INTEL_PANTHERLAKE_BASE
	bool
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
	select ARCH_X86
	select BOOT_DEVICE_SUPPORTS_WRITES
	select CACHE_MRC_SETTINGS
	select CPU_INTEL_COMMON
	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
	select FSP_M_XIP
	select FSP_USES_CB_DEBUG_EVENT_HANDLER
	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
	select HAVE_X86_64_SUPPORT
	select IDT_IN_EVERY_STAGE
	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
	select INTEL_DESCRIPTOR_MODE_CAPABLE
	select IOAPIC
	select MICROCODE_BLOB_UNDISCLOSED
	select MRC_SETTINGS_PROTECT
	select PLATFORM_USES_FSP2_4
	select SOC_INTEL_COMMON
	select SOC_INTEL_COMMON_BLOCK
	select SOC_INTEL_COMMON_BLOCK_CAR
	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
	select SOC_INTEL_COMMON_BLOCK_CPU
	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
	select SOC_INTEL_COMMON_BLOCK_IOE_P2SB
	select SOC_INTEL_COMMON_BLOCK_MEMINIT
	select SOC_INTEL_COMMON_BLOCK_SA
	select SOC_INTEL_COMMON_PCH_CLIENT
	select SOC_INTEL_COMMON_RESET
	select SOC_INTEL_IOE_DIE_SUPPORT
	select SSE2
	select SUPPORT_CPU_UCODE_IN_CBFS
	select TSC_MONOTONIC_TIMER
	select UDELAY_TSC
	select UDK_202302_BINDING
	select USE_X86_64_SUPPORT
	help
	  Intel Pantherlake support. Mainboards should specify the SoC
	  type using the `SOC_INTEL_PANTHERLAKE_*` options instead
	  of selecting this option directly.

config SOC_INTEL_PANTHERLAKE_U_H
	bool
	select SOC_INTEL_PANTHERLAKE_BASE
	help
	  Choose this option if the mainboard is built using either a PTL-U (15W) or
	  PTL-H 12Xe (25W) system-on-a-chip SoC.
	  Note, PTL U/H processor line is offered in a single package platform that includes the
	  Compute tile, the PCD tile, and the GFX tile on the same package.

config SOC_INTEL_PANTHERLAKE_H
	bool
	depends on !SOC_INTEL_PANTHERLAKE_U_H
	select SOC_INTEL_PANTHERLAKE_BASE
	help
	  Choose this option if the mainboard is built using PTL-H 4Xe system-on-a-chip (SoC).
	  Note, PTL-H processor line is offered in a single package platform that includes the
	  Compute tile, the PCD tile, and the GFX tile on the same package.

if SOC_INTEL_PANTHERLAKE_BASE

config CAR_ENHANCED_NEM
	bool
	default y if !INTEL_CAR_NEM
	select INTEL_CAR_NEM_ENHANCED
	select CAR_HAS_SF_MASKS
	select COS_MAPPED_TO_MSB
	select CAR_HAS_L3_PROTECTED_WAYS

config MAX_CPUS
	int
	default 16

config DCACHE_RAM_BASE
	default 0xfef00000

config DCACHE_RAM_SIZE
	default 0xc0000
	help
	  The size of the cache-as-ram region required during bootblock
	  and/or romstage.

config DCACHE_BSP_STACK_SIZE
	hex
	default 0x88000
	help
	  The amount of anticipated stack usage in CAR by bootblock and
	  other stages. In the case of FSP_USES_CB_STACK default value will be
	  sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
	  (~32KiB).

config FSP_TEMP_RAM_SIZE
	hex
	default 0x20000
	help
	  The amount of anticipated heap usage in CAR by FSP.
	  Refer to Platform FSP integration guide document to know
	  the exact FSP requirement for Heap setup.

config IFD_CHIPSET
	string
	default "ptl"

config IED_REGION_SIZE
	hex
	default 0x400000

config MAX_TBT_ROOT_PORTS
	int
	default 4

config MAX_ROOT_PORTS
	int
	default 10 if SOC_INTEL_PANTHERLAKE_H
	default 12

config MAX_PCIE_CLOCK_SRC
	int
	default 9

config PCR_BASE_ADDRESS
	hex
	default 0x4000000000
	help
	  This option allows you to select MMIO Base Address of P2SB#1 aka SoC P2SB.

config P2SB_2_PCR_BASE_ADDRESS
	hex
	default 0x4010000000
	help
	  This option allows you to select MMIO Base Address of P2SB#2 aka SoC P2SB2.

config ECAM_MMCONF_BASE_ADDRESS
	default 0xe0000000

config CPU_BCLK_MHZ
	int
	default 100

config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
	int
	default 120

config CPU_XTAL_HZ
	default 38400000

config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
	int
	default 133

config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
	int
	default 3

config SOC_INTEL_I2C_DEV_MAX
	int
	default 6

config SOC_INTEL_UART_DEV_MAX
	int
	default 3

config SOC_INTEL_USB2_DEV_MAX
	int
	default 8

config SOC_INTEL_USB3_DEV_MAX
	int
	default 2

config CONSOLE_UART_BASE_ADDRESS
	hex
	default 0xfe02c000
	depends on INTEL_LPSS_UART_FOR_CONSOLE

# Clock divider parameters for 115200 baud rate
# Baudrate = (UART source clcok * M) /(N *16)
# PTL UART source clock: 100MHz
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
	hex
	default 0x25a

config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
	hex
	default 0x7fff

config VBOOT
	select VBOOT_SEPARATE_VERSTAGE
	select VBOOT_MUST_REQUEST_DISPLAY
	select VBOOT_STARTS_IN_BOOTBLOCK
	select VBOOT_VBNV_CMOS
	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
	select VBOOT_X86_SHA256_ACCELERATION

# Default hash block size is 1KiB. Increasing it to 4KiB to improve
# hashing time as well as read time.
config VBOOT_HASH_BLOCK_SIZE
	hex
	default 0x1000

config CBFS_SIZE
	hex
	default 0x200000

config PRERAM_CBMEM_CONSOLE_SIZE
	hex
	default 0x2000

config CONSOLE_CBMEM_BUFFER_SIZE
	hex
	default 0x100000 if BUILDING_WITH_DEBUG_FSP
	default 0x40000

config FSP_HEADER_PATH
	string "Location of FSP headers"
	default "src/vendorcode/intel/fsp/fsp2_0/pantherlake/"

# Override platform debug consent value:
#  0: Disabled,
#  2: Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix,
#  4: Enabled Trace ready: TraceHub is enabled and allowed S0ix,
#  6: Enabled Trace power off: TraceHub is powergated, provide setting close to functional
#    low power state,
#  7: User needs to configure Advanced Debug Settings manually.
config SOC_INTEL_COMMON_DEBUG_CONSENT
	int
	default 4 if SOC_INTEL_DEBUG_CONSENT

config DATA_BUS_WIDTH
	int
	default 128

config DIMMS_PER_CHANNEL
	int
	default 2

config MRC_CHANNEL_WIDTH
	int
	default 16

config BUILDING_WITH_DEBUG_FSP
	bool "Debug FSP is used for the build"
	default n
	help
	  Set this option if debug build of FSP is used.

config FSP_PUBLISH_MBP_HOB
	bool
	default n if CHROMEOS
	default y
	help
	  This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
	  Disabling it for the platforms, which do not use MBP HOB, can improve the boot time.

endif