config SOC_INTEL_FSP_BROADWELL_DE
	bool
	help
	  Broadwell-DE support using the Intel FSP.

if SOC_INTEL_FSP_BROADWELL_DE

config CPU_SPECIFIC_OPTIONS
	def_bool y
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
	select ARCH_BOOTBLOCK_X86_32
	select ARCH_VERSTAGE_X86_32
	select ARCH_ROMSTAGE_X86_32
	select ARCH_RAMSTAGE_X86_32
	select SOUTHBRIDGE_INTEL_COMMON_RESET
	select NO_RELOCATABLE_RAMSTAGE
	select PARALLEL_MP
	select SMP
	select IOAPIC
	select SPI_FLASH
	select UDELAY_TSC
	select SUPPORT_CPU_UCODE_IN_CBFS
	# Microcode header files are delivered in FSP package
	select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
	select INTEL_DESCRIPTOR_MODE_CAPABLE
	select SMM_TSEG
	select HAVE_SMI_HANDLER
	select TSC_MONOTONIC_TIMER
	select TSC_CONSTANT_RATE

config CBFS_SIZE
	hex
	default 0x200000

config HEAP_SIZE
	hex
	default 0x100000

config BOOTBLOCK_CPU_INIT
	string
	default "soc/intel/fsp_broadwell_de/bootblock/bootblock.c"

config MMCONF_BASE_ADDRESS
	hex
	default 0x80000000

config MAX_CPUS
	int
	default 32

config CPU_ADDR_BITS
	int
	default 36

config VGA_BIOS
	bool
	default n

config SMM_TSEG_SIZE
	hex
	default 0x800000

config SMM_RESERVED_SIZE
	hex
	default 0x100000

config INTEGRATED_UART
	bool "Integrated UART ports"
	default y
	select DRIVERS_UART_8250IO
	select DRIVERS_UART_8250IO_SKIP_INIT
	select CONSOLE_SERIAL
	help
	  Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.

config CONSOLE_CBMEM
	bool "Send console output to a CBMEM buffer"
	default n

config CPU_MICROCODE_HEADER_FILES
	string
	default "../intel/cpu/broadwell_de/microcode/M1050663_07000001.h ../intel/cpu/broadwell_de/microcode/M1050662_0000000A.h ../intel/cpu/broadwell_de/microcode/MFF50661_F1000008.h"

config SERIRQ_CONTINUOUS_MODE
	bool
	default n
	help
	  If you set this option to y, the serial IRQ machine will be
	  operated in continuous mode.

## Broadwell-DE Specific FSP Kconfig
source src/soc/intel/fsp_broadwell_de/fsp/Kconfig

endif	# SOC_INTEL_FSP_BROADWELL_DE