## SPDX-License-Identifier: GPL-2.0-only

config SOC_INTEL_COMMON_BLOCK_ACPI
	depends on SOC_INTEL_COMMON_BLOCK_CPU
	depends on SOC_INTEL_COMMON_BLOCK_PMC
	select ACPI_COMMON_MADT_IOAPIC
	select ACPI_COMMON_MADT_LAPIC if !SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
	select ACPI_CUSTOM_MADT
	bool
	help
	  Intel Processor common code for ACPI

config SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
	bool

config SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
	bool
	depends on HAVE_ACPI_TABLES
	select ACPI_LPIT
	help
	  Generate LPIT table with LPI state entries

config SOC_INTEL_COMMON_BLOCK_ACPI_PEP
	bool
	depends on HAVE_ACPI_TABLES
	help
	  Generate an Intel Power Engine device object in the SSDT. This is
	  usually used for providing ACPI hooks for S0ix exit/entry.

config SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
	bool
	depends on SOC_INTEL_COMMON_BLOCK_ACPI_PEP
	help
	  Generate a 2nd set of _DSM functions for the Power Engine device that
	  will return a buffer that contains the contents of the PMC's LPM
	  requirements registers. A kernel can use this to display the
	  requirements for different LPM substates.

config SOC_INTEL_COMMON_BLOCK_CRASHLOG
	bool
	depends on SOC_INTEL_CRASHLOG
	help
	  Generate crash data for BERT table

if SOC_INTEL_COMMON_BLOCK_ACPI

config SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
	bool
	help
	  Generate CPPC entries for Intel SpeedShift

config SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
	bool
	help
	  Defines hybrid CPU specific ACPI helper functions.

config SOC_INTEL_UFS_OCP_TIMER_DISABLE
	bool
	help
	  OCP Timer need to be disabled in SCS UFS IOSF Bridge to
	  work around the Silicon Issue due to which LTR mechanism
	  doesn't work.

config SOC_INTEL_UFS_LTR_DISQUALIFY
	bool
	help
	  LTR needs to be disqualified for UFS in D3 to ensure PMC
	  ignores LTR from UFS IP which is infinite.
endif

if SOC_INTEL_COMMON_BLOCK_ACPI_LPIT

config SOC_INTEL_COMMON_BLOCK_ACPI_SLP_S0_FREQ_HZ
	hex
	help
	  Define the slp_s0_residency frequency to be reported in the
	  LPIT ACPI table.

config SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1
	bool "Use GPE1 Event bits"
	help
	  Include GPE1 STS and EN registers in FADT. Requires define GPE1_STS(0)
	  and GPE1_REG_MAX from the SOC header. The SOC needs to have GPE1 block
	  implemented to select this. This flag will also be used to determine the
	  standard GPE0/1 event methods to use in the ASL code or devicetree for the
	  internal wake capable devices. GPE1 Event Bit is an extension of GPE0
	  (present in all Intel SoC platform). GPE1 Events include the power
	  management, hot plug, and PCIe events for the internal devices. Select
	  this Kconfig to support SoCs that publish GPE1 as part of PMC IO register.

endif