config SOC_INTEL_BAYTRAIL bool help Bay Trail M/D part support. if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select REG_SCRIPT select SMM_TSEG select SMP select SPI_FLASH select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC select SOC_INTEL_COMMON select HAVE_INTEL_FIRMWARE select HAVE_SPI_CONSOLE_SUPPORT config BOOTBLOCK_CPU_INIT string default "soc/intel/baytrail/bootblock/bootblock.c" config MMCONF_BASE_ADDRESS hex default 0xe0000000 config MAX_CPUS int default 4 config CPU_ADDR_BITS int default 36 config SMM_TSEG_SIZE hex default 0x800000 config SMM_RESERVED_SIZE hex default 0x100000 config HAVE_MRC bool "Add a Memory Reference Code binary" default y help Select this option to add a blob containing memory reference code. Note: Without this binary coreboot will not work if HAVE_MRC config MRC_FILE string "Intel memory refeference code path and filename" default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin" help The path and filename of the file to use as System Agent binary. Note that this points to the sandybridge binary file which is will not work, but it serves its purpose to do builds. config MRC_BIN_ADDRESS hex default 0xfffa0000 config MRC_RMT bool "Enable MRC RMT training + debug prints" default n endif # HAVE_MRC # Cache As RAM region layout: # # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE # | MRC usage | # | | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE # | Stack |\ # | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE # | v |/ # +-------------+ # | ^ | # | | | # | CAR Globals | # +-------------+ DCACHE_RAM_BASE # # Note that the MRC binary is linked to assume the region marked as "MRC usage" # starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then # a new MRC binary needs to be produced with the updated start and size # information. config DCACHE_RAM_BASE hex default 0xfe000000 config DCACHE_RAM_SIZE hex default 0x8000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. config DCACHE_RAM_MRC_VAR_SIZE hex default 0x8000 help The amount of cache-as-ram region required by the reference code. config DCACHE_RAM_ROMSTAGE_STACK_SIZE hex default 0x800 help The amount of anticipated stack usage from the data cache during pre-RAM ROM stage execution. config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n depends on RELOCATABLE_RAMSTAGE help The baytrail romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs. config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n help The PMC has a legacy COM1 serial port. Choose this option to configure the pads and enable it. This serial port can be used for the debug console. config HAVE_REFCODE_BLOB depends on ARCH_X86 bool "An external reference code blob should be put into cbfs." default n help The reference code blob will be placed into cbfs. if HAVE_REFCODE_BLOB config REFCODE_BLOB_FILE string "Path and filename to reference code blob." default "refcode.elf" help The path and filename to the file to be added to cbfs. endif # HAVE_REFCODE_BLOB config CHIPSET_BOOTBLOCK_INCLUDE string default "soc/intel/baytrail/bootblock/timestamp.inc" endif