/* This file is part of the coreboot project. */ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include #include #include #include #include #include #include #include #include #include #include #include uintptr_t fsp_soc_get_igd_bar(void) { return graphics_get_memory_base(); } void graphics_soc_init(struct device *const dev) { if (CONFIG(RUN_FSP_GOP)) return; uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, reg32); if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { if (!acpi_is_wakeup_s3() && display_init_required()) { int lightup_ok; gma_gfxinit(&lightup_ok); gfx_set_init_done(lightup_ok); } } else { /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); } } uintptr_t graphics_soc_write_acpi_opregion(const struct device *device, uintptr_t current, struct acpi_rsdp *rsdp) { igd_opregion_t *opregion; printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); opregion = (igd_opregion_t *)current; if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) return current; /* FIXME: Add platform specific mailbox initialization */ current += sizeof(igd_opregion_t); return acpi_align_current(current); }