/* * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. * (Written by Andrey Petrov for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static const struct pad_config tpm_spi_configs[] = { PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ }; static void tpm_enable(void) { /* Configure gpios */ gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs)); } asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { device_t dev; bootblock_systemagent_early_init(); dev = PCH_DEV_P2SB; /* BAR and MMIO enable for PCR-Space, so that GPIOs can be configured */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Decode the ACPI I/O port range for early firmware verification.*/ dev = PCH_DEV_PMC; pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER); enable_rtc_upper_bank(); /* Call lib/bootblock.c main */ bootblock_main_with_timestamp(base_timestamp); } static void cache_bios_region(void) { int mtrr; size_t rom_size; uint32_t alignment; mtrr = get_free_var_mtrr(); if (mtrr == -1) return; /* Only the IFD BIOS region is memory mapped (at top of 4G) */ rom_size = get_bios_size(); if (!rom_size) return; /* Round to power of two */ alignment = 1 << (log2_ceil(rom_size)); rom_size = ALIGN_UP(rom_size, alignment); set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT); } static void enable_pmcbar(void) { device_t pmc = PCH_DEV_PMC; /* Set PMC base addresses and enable decoding. */ pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); pci_write_config16(pmc, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } void bootblock_soc_early_init(void) { enable_pmcbar(); /* Clear global reset promotion bit */ global_reset_enable(0); /* Prepare UART for serial console. */ if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) pch_uart_init(); if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI)) tpm_enable(); enable_pm_timer_emulation(); fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS); cache_bios_region(); /* Initialize GPE for use as interrupt status */ pmc_gpe_init(); }