config SOC_INTEL_APOLLOLAKE bool help Intel Apollolake support config SOC_INTEL_GLK bool default n select SOC_INTEL_APOLLOLAKE select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select IDT_IN_EVERY_STAGE select PAGING_IN_CACHE_AS_RAM help Intel GLK support if SOC_INTEL_APOLLOLAKE config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC select PCR_COMMON_IOSF_1_0 select SMP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS # Audio options select ACPI_NHLT select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select COMMON_FADT select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select GENERIC_GPIO_LIB select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select MRC_SETTINGS_PROTECT select MRC_SETTINGS_VARIABLE_DATA select NO_FIXED_XIP_ROM_SIZE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PARALLEL_MP_AP_WORK select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE select PCIEX_LENGTH_256MB select POSTCAR_CONSOLE select POSTCAR_STAGE select PMC_INVALID_READ_AFTER_WRITE select PMC_GLOBAL_RESET_ENABLE_LOCK select REG_SCRIPT select RTC select SMM_TSEG select SA_ENABLE_IMR select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_DSP select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GRAPHICS select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_I2C select SOC_INTEL_COMMON_BLOCK_LPC select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER select HAVE_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 select UDK_2015_BINDING if !SOC_INTEL_GLK select UDK_2017_BINDING if SOC_INTEL_GLK select HAVE_HARD_RESET select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select HAVE_FSP_GOP select NO_UART_ON_SUPERIO select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_OPROM_MATTERS select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH config TPM_ON_FAST_SPI bool default n depends on MAINBOARD_HAS_LPC_TPM help TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface. config SOC_INTEL_COMMON_RESET bool default y config PCR_BASE_ADDRESS hex default 0xd0000000 help This option allows you to select MMIO Base Address of sideband bus. config DCACHE_RAM_BASE hex default 0xfef00000 config DCACHE_RAM_SIZE hex default 0x100000 if SOC_INTEL_GLK default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and other stages. config CPU_ADDR_BITS int default 39 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 100 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 config UART_DEBUG bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE." default n select CONSOLE_SERIAL select DRIVERS_UART select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. config C_ENV_BOOTBLOCK_SIZE hex default 0x8000 # This SoC does not map SPI flash like many previous SoC. Therefore we provide # a custom media driver that facilitates mapping config X86_TOP4G_BOOTMEDIA_MAP bool default n config ROMSTAGE_ADDR hex default 0xfef20000 help The base address (in CAR) where romstage should be linked config VERSTAGE_ADDR hex default 0xfef40000 help The base address (in CAR) where verstage should be linked config FSP_HEADER_PATH string default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GLK default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/" config FSP_FD_PATH string depends on FSP_USE_REPO default "3rdparty/fsp/ApolloLakeFspBinPkg/FspBin/Fsp.fd" config FSP_M_ADDR hex default 0xfef40000 help The address FSP-M will be relocated to during build time config NEED_LBP2 bool "Write contents for logical boot partition 2." default n help Write the contents from a file into the logical boot partition 2 region defined by LBP2_FMAP_NAME. config LBP2_FMAP_NAME string "Name of FMAP region to put logical boot partition 2" depends on NEED_LBP2 default "SIGN_CSE" help Name of FMAP region to write logical boot partition 2 data. config LBP2_FILE_NAME string "Path of file to write to logical boot partition 2 region" depends on NEED_LBP2 default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin" help Name of file to store in the logical boot partition 2 region. config NEED_IFWI bool "Write content into IFWI region" default n help Write the content from a file into IFWI region defined by IFWI_FMAP_NAME. config IFWI_FMAP_NAME string "Name of FMAP region to pull IFWI into" depends on NEED_IFWI default "IFWI" help Name of FMAP region to write IFWI. config IFWI_FILE_NAME string "Path of file to write to IFWI region" depends on NEED_IFWI default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" help Name of file to store in the IFWI region. config HEAP_SIZE hex default 0x8000 config NHLT_DMIC_1CH_16B bool depends on ACPI_NHLT default n help Include DSP firmware settings for 1 channel 16B DMIC array. config NHLT_DMIC_2CH_16B bool depends on ACPI_NHLT default n help Include DSP firmware settings for 2 channel 16B DMIC array. config NHLT_DMIC_4CH_16B bool depends on ACPI_NHLT default n help Include DSP firmware settings for 4 channel 16B DMIC array. config NHLT_MAX98357 bool depends on ACPI_NHLT default n help Include DSP firmware settings for headset codec. config NHLT_DA7219 bool depends on ACPI_NHLT default n help Include DSP firmware settings for headset codec. config NHLT_RT5682 bool depends on ACPI_NHLT default n help Include DSP firmware settings for headset codec. choice prompt "Cache-as-ram implementation" default CAR_CQOS if !SOC_INTEL_GLK default CAR_NEM help This option allows you to select how cache-as-ram (CAR) is set up. config CAR_NEM bool "Non-evict mode" select SOC_INTEL_COMMON_BLOCK_CAR select INTEL_CAR_NEM help Traditionally, CAR is set up by using Non-Evict mode. This method does not allow CAR and cache to co-exist, because cache fills are block in NEM mode. config CAR_CQOS bool "Cache Quality of Service" select SOC_INTEL_COMMON_BLOCK_CAR select INTEL_CAR_CQOS help Cache Quality of Service allows more fine-grained control of cache usage. As result, it is possible to set up portion of L2 cache for CAR and use remainder for actual caching. config USE_APOLLOLAKE_FSP_CAR bool "Use FSP CAR" select FSP_CAR help Use FSP APIs to initialize & tear down the Cache-As-Ram. endchoice # # Each bit in QOS mask controls this many bytes. This is calculated as: # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS # config CACHE_QOS_SIZE_PER_BIT hex default 0x20000 # 128 KB config L2_CACHE_SIZE hex default 0x400000 if SOC_INTEL_GLK default 0x100000 config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n config SMM_RESERVED_SIZE hex default 0x100000 config IFD_CHIPSET string default "glk" if SOC_INTEL_GLK default "aplk" config CPU_BCLK_MHZ int default 100 config APL_SKIP_SET_POWER_LIMITS bool default n help Some Apollo Lake mainboards do not need the Running Average Power Limits (RAPL) algorithm for a constant power management. Set this config option to skip the RAPL configuration. # M and N divisor values for clock frequency configuration. # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex default 0x25a config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL hex default 0x7fff config SOC_ESPI bool default n help Use eSPI bus instead of LPC config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 3 config SOC_INTEL_I2C_DEV_MAX int default 8 # Don't include the early page tables in RW_A or RW_B cbfs regions config RO_REGION_ONLY string default "pdpt pt" endif