config SOC_INTEL_ALDERLAKE bool help Intel Alderlake support. Mainboards should specify the PCH type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead of selecting this option directly. config SOC_INTEL_RAPTORLAKE bool select X86_INIT_NEED_1_SIPI help Intel Raptorlake support. Mainboards using RPL should select SOC_INTEL_RAPTORLAKE and SOC_INTEL_ALDERLAKE_PCH_* together. config SOC_INTEL_ALDERLAKE_PCH_M bool select SOC_INTEL_ALDERLAKE help Choose this option if your mainboard has a PCH-M chipset. config SOC_INTEL_ALDERLAKE_PCH_N bool select SOC_INTEL_ALDERLAKE select MICROCODE_BLOB_UNDISCLOSED help Choose this option if your mainboard has a PCH-N chipset. config SOC_INTEL_ALDERLAKE_PCH_P bool select SOC_INTEL_ALDERLAKE select HAVE_INTEL_FSP_REPO select PLATFORM_USES_FSP2_3 help Choose this option if your mainboard has a PCH-P chipset. config SOC_INTEL_ALDERLAKE_PCH_S bool select SOC_INTEL_ALDERLAKE select HAVE_INTEL_FSP_REPO select PLATFORM_USES_FSP2_3 help Choose this option if your mainboard has a PCH-S chipset. if SOC_INTEL_ALDERLAKE config CPU_SPECIFIC_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_ADL_IPU_ES_SUPPORT select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_INTEL_TME select CPU_SUPPORTS_PM_TIMER_EMULATION select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS select DISPLAY_FSP_VERSION_INFO select DRIVERS_USB_ACPI select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_COMPRESS_FSP_S_LZ4 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_M_XIP select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select FSP_USES_CB_DEBUG_EVENT_HANDLER select FSPS_HAS_ARCH_UPD select GENERIC_GPIO_LIB select HAVE_DEBUG_RAM_SETUP select HAVE_FSP_GOP select HAVE_HYPERTHREADING select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_OPREGION_2_1 select INTEL_TXT_LIB select MP_SERVICES_PPI_V2 select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_2 select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select CPU_INTEL_COMMON_VOLTAGE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BASECODE_RAMTOP select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BLOCK_IPU if !SOC_INTEL_ALDERLAKE_PCH_S select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC select SOC_INTEL_COMMON_BLOCK_VTD select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select HAVE_INTEL_COMPLIANCE_TEST_MODE select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202005_BINDING select VBOOT_LIB select X86_CLFLUSH_CAR config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT bool default y if !SOC_INTEL_ALDERLAKE_PCH_S default n if SOC_INTEL_ALDERLAKE_PCH_S select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI config ALDERLAKE_CONFIGURE_DESCRIPTOR bool help Select this if the descriptor needs to be updated at runtime. This can only be done if the descriptor region is writable, and should only be used as a temporary workaround. config ALDERLAKE_CAR_ENHANCED_NEM bool default y if !INTEL_CAR_NEM select INTEL_CAR_NEM_ENHANCED select CAR_HAS_SF_MASKS select COS_MAPPED_TO_MSB select CAR_HAS_L3_PROTECTED_WAYS config MAX_CPUS int default 32 if SOC_INTEL_RAPTORLAKE default 24 config DCACHE_RAM_BASE default 0xfef00000 config DCACHE_RAM_SIZE default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex default 0x80400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE hex default 0x20000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. config CHIPSET_DEVICETREE string default "soc/intel/alderlake/chipset_pch_s.cb" if SOC_INTEL_ALDERLAKE_PCH_S default "soc/intel/alderlake/chipset.cb" config EXT_BIOS_WIN_BASE default 0xf8000000 config EXT_BIOS_WIN_SIZE default 0x2000000 config IFD_CHIPSET string default "adl" config IED_REGION_SIZE hex default 0x400000 config HEAP_SIZE hex default 0x10000 config GFX_GMA_DEFAULT_MMIO default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT # Intel recommends reserving the following resources per PCIe TBT root port, # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 # - 42 buses # - 194 MiB Non-prefetchable memory # - 448 MiB Prefetchable memory if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config PCIEXP_HOTPLUG_BUSES int default 42 config PCIEXP_HOTPLUG_MEM hex default 0xc200000 config PCIEXP_HOTPLUG_PREFETCH_MEM hex default 0x1c000000 endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config MAX_PCH_ROOT_PORTS int default 10 if SOC_INTEL_ALDERLAKE_PCH_M default 12 if SOC_INTEL_ALDERLAKE_PCH_N default 12 if SOC_INTEL_ALDERLAKE_PCH_P default 28 if SOC_INTEL_ALDERLAKE_PCH_S config MAX_CPU_ROOT_PORTS int default 1 if SOC_INTEL_ALDERLAKE_PCH_M default 0 if SOC_INTEL_ALDERLAKE_PCH_N default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S config MAX_TBT_ROOT_PORTS int default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S default 2 if SOC_INTEL_ALDERLAKE_PCH_M default 4 if SOC_INTEL_ALDERLAKE_PCH_P config MAX_ROOT_PORTS int default MAX_PCH_ROOT_PORTS config MAX_PCIE_CLOCK_SRC int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 10 if SOC_INTEL_ALDERLAKE_PCH_P default 18 if SOC_INTEL_ALDERLAKE_PCH_S help With external clock buffer, Alderlake-P can support up to three additional source clocks. This is done by setting the corresponding GPIO pin(s) to native function to use as SRCCLK_OE[6..9]. In addition, SRCCLK6 does not need to be set to free running clock. If any of SRCCLKReq 6..9 is asserted, SRCCLK6 will be turned on. config MAX_PCIE_CLOCK_REQ int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 10 if SOC_INTEL_ALDERLAKE_PCH_P default 18 if SOC_INTEL_ALDERLAKE_PCH_S config SMM_TSEG_SIZE hex default 0x800000 config SMM_RESERVED_SIZE hex default 0x200000 config PCR_BASE_ADDRESS hex default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S default 0xfd000000 help This option allows you to select MMIO Base Address of sideband bus. config ECAM_MMCONF_BASE_ADDRESS default 0xc0000000 config CPU_BCLK_MHZ int default 100 config SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR int default 127 config SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR int default 100 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 120 config CPU_XTAL_HZ default 38400000 config SOC_INTEL_UFS_CLK_FREQ_HZ int default 19200000 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX int default 7 config SOC_INTEL_I2C_DEV_MAX int default 8 config ENABLE_SATA_TEST_MODE bool "Enable test mode for SATA margining" default n help Enable SATA test mode in FSP-S. config SOC_INTEL_UART_DEV_MAX int default 7 config CONSOLE_UART_BASE_ADDRESS hex default 0xfe03e000 depends on INTEL_LPSS_UART_FOR_CONSOLE config VBT_DATA_SIZE_KB int default 9 # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clock * M) /(N *16) # ADL UART source clock: 100MHz config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex default 0x25a config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL hex default 0x7fff config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH select VBOOT_X86_SHA256_ACCELERATION # Default hash block size is 1KiB. Increasing it to 4KiB to improve # hashing time as well as read time. This helps in improving # boot time for Alder Lake. config VBOOT_HASH_BLOCK_SIZE hex default 0x1000 config CBFS_SIZE default 0x200000 config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x16000 if CONSOLE_SERIAL default 0x4000 config CONSOLE_CBMEM_BUFFER_SIZE hex default 0x100000 if CONSOLE_SERIAL default 0x40000 config FSP_TYPE_IOT bool default n help This option allows to select FSP IOT type from 3rdparty/fsp repo config FSP_HEADER_PATH string "Location of FSP headers" default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" config FSP_FD_PATH string depends on FSP_USE_REPO default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT int "Debug Consent for ADL" # USB DBC is more common for developers so make this default to 2 if # SOC_INTEL_DEBUG_CONSENT=y default 2 if SOC_INTEL_DEBUG_CONSENT default 0 help This is to control debug interface on SOC. Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details. Desired platform debug type are 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual config DATA_BUS_WIDTH int default 128 config DIMMS_PER_CHANNEL int default 2 config MRC_CHANNEL_WIDTH int default 16 config ACPI_ADL_IPU_ES_SUPPORT def_bool n help Enables ACPI entry to provide silicon type information to IPU kernel driver. config ALDERLAKE_ENABLE_SOC_WORKAROUND bool default y select SOC_INTEL_UFS_LTR_DISQUALIFY select SOC_INTEL_UFS_OCP_TIMER_DISABLE help Selects the workarounds applicable for Alder Lake SoC. config USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS bool help Alder Lake SoC based OEM board design with UFS and non-UFS planned to use an unified AP firmware which demanded to have a unified descriptor. It means UFS controller needs to default fuse enabled to let UFS SKU to boot. On such design with non-UFS SKU is exhibiting S0ix failure due to UFS remain enabled in the strap although FSP-S is making the UFS controller function disabled. The potential root cause of this behaviour is although the UFS controller is function disabled but MPHY clock is still in active state. A possible solution to this problem is to issue a warm reboot (if boot path is S5->S0 or G3->S0) after disabling the UFS and let PMC to read the function disable state of the UFS for disabling the MPHY clock. Mainboard users with such board design where OEM would like to use an unified AP firmware to support both UFS and non-UFS sku booting might need to choose this config to allow disabling UFS while booting on the non-UFS SKU. Note: selection of this config would introduce an additional warm reset in cold-reset scenarios due to function disabling of the UFS controller. if STITCH_ME_BIN config CSE_BPDT_VERSION default "1.7" endif config SI_DESC_REGION string "Descriptor Region name" default "SI_DESC" help Name of Descriptor Region in the FMAP config SI_DESC_REGION_SZ int default 4096 help Size of Descriptor Region in the FMAP config BUILDING_WITH_DEBUG_FSP bool "Debug FSP is used for the build" default n help Set this option if debug build of FSP is used. config INTEL_GMA_BCLV_OFFSET default 0xc8258 config INTEL_GMA_BCLV_WIDTH default 32 config INTEL_GMA_BCLM_OFFSET default 0xc8254 config INTEL_GMA_BCLM_WIDTH default 32 config FSP_PUBLISH_MBP_HOB bool default n if CHROMEOS && (SOC_INTEL_RAPTORLAKE || SOC_INTEL_ALDERLAKE_PCH_N) default y help This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. Disabling it for the platforms, which do not use MBP HOB, can improve the boot time. Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based platforms. endif