# SPDX-License-Identifier: GPL-2.0-only # TODO: Evaluate what can be moved to a common directory # TODO: Update for Glinda config SOC_AMD_GLINDA bool select ACPI_SOC_NVS select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI select DRIVERS_USB_PCI_XHCI select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING select FSP_COMPRESS_FSP_M_LZ4 if ASYNC_FILE_LOADING select FSP_COMPRESS_FSP_S_LZ4 select GENERIC_GPIO_LIB select HAVE_ACPI_TABLES select HAVE_CF9_RESET select HAVE_EM100_SUPPORT select HAVE_FSP_GOP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK select RESET_VECTOR_IN_RAM select RTC select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACP_GEN2 # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPIMMIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_CPPC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_AOAC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMU # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SSE2 select UDK_2017_BINDING select USE_DDR5 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select VBOOT_DEFINE_WIDEVINE_COUNTERS if VBOOT_STARTS_BEFORE_BOOTBLOCK select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI help AMD Glinda support if SOC_AMD_GLINDA config CHIPSET_DEVICETREE string default "soc/amd/glinda/chipset.cb" config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 help This variable defines the base address of the DRAM which is reserved for usage by coreboot in early stages (i.e. before ramstage is up). This memory gets reserved in BIOS tables to ensure that the OS does not use it, thus preventing corruption of OS memory in case of S3 resume. config EARLYRAM_BSP_STACK_SIZE hex default 0x1000 config PSP_APOB_DRAM_ADDRESS hex default 0x2001000 help Location in DRAM where the PSP will copy the AGESA PSP Output Block. config PSP_APOB_DRAM_SIZE hex default 0x1E000 config PSP_SHAREDMEM_BASE hex default 0x201F000 if VBOOT default 0x0 help This variable defines the base address in DRAM memory where PSP copies the vboot workbuf. This is used in the linker script to have a static allocation for the buffer as well as for adding relevant entries in the BIOS directory table for the PSP. config PSP_SHAREDMEM_SIZE hex default 0x8000 if VBOOT default 0x0 help Sets the maximum size for the PSP to pass the vboot workbuf and any logs or timestamps back to coreboot. This will be copied into main memory by the PSP and will be available when the x86 is started. The workbuf's base depends on the address of the reset vector. config PRE_X86_CBMEM_CONSOLE_SIZE hex default 0x1600 help Size of the CBMEM console used in PSP verstage. config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1600 help Increase this value if preram cbmem console is getting truncated config CBFS_MCACHE_SIZE hex default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 help Sets the size of the bootblock stage that should be loaded in DRAM. This variable controls the DRAM allocation size in linker script for bootblock stage. config ROMSTAGE_ADDR hex default 0x2040000 help Sets the address in DRAM where romstage should be loaded. config ROMSTAGE_SIZE hex default 0x80000 help Sets the size of DRAM allocation for romstage in linker script. config FSP_M_ADDR hex default 0x20C0000 help Sets the address in DRAM where FSP-M should be loaded. cbfstool performs relocation of FSP-M to this address. config FSP_M_SIZE hex default 0xC0000 help Sets the size of DRAM allocation for FSP-M in linker script. config FSP_TEMP_RAM_SIZE hex default 0x40000 help The amount of coreboot-allocated heap and stack usage by the FSP. config VERSTAGE_ADDR hex depends on VBOOT_SEPARATE_VERSTAGE default 0x2180000 help Sets the address in DRAM where verstage should be loaded if running as a separate stage on x86. config VERSTAGE_SIZE hex depends on VBOOT_SEPARATE_VERSTAGE default 0x80000 help Sets the size of DRAM allocation for verstage in linker script if running as a separate stage on x86. config ASYNC_FILE_LOADING bool "Loads files from SPI asynchronously" select COOP_MULTITASKING select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA select CBFS_PRELOAD help When enabled, the platform will use the LPC SPI DMA controller to asynchronously load contents from the SPI ROM. This will improve boot time because the CPUs can be performing useful work while the SPI contents are being preloaded. config CBFS_CACHE_SIZE hex default 0x40000 if CBFS_PRELOAD config RO_REGION_ONLY string depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A default "apu/amdfw" config ECAM_MMCONF_BASE_ADDRESS default 0xF8000000 config ECAM_MMCONF_BUS_NUMBER default 64 config MAX_CPUS int default 8 if SOC_AMD_GLINDA default 16 help Maximum number of threads the platform can have. config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART hex default 0xfedc9000 if UART_FOR_CONSOLE = 0 default 0xfedca000 if UART_FOR_CONSOLE = 1 default 0xfedce000 if UART_FOR_CONSOLE = 2 default 0xfedcf000 if UART_FOR_CONSOLE = 3 default 0xfedd1000 if UART_FOR_CONSOLE = 4 config SMM_TSEG_SIZE hex default 0x800000 if HAVE_SMI_HANDLER default 0x0 config SMM_RESERVED_SIZE hex default 0x180000 config SMM_MODULE_STACK_SIZE hex default 0x800 config ACPI_BERT bool "Build ACPI BERT Table" default y depends on HAVE_ACPI_TABLES help Report Machine Check errors identified in POST to the OS in an ACPI Boot Error Record Table. config ACPI_BERT_SIZE hex default 0x4000 if ACPI_BERT default 0x0 help Specify the amount of DRAM reserved for gathering the data used to generate the ACPI table. config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 150 config DISABLE_SPI_FLASH_ROM_SHARING def_bool n help Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin which indicates a board level ROM transaction request. This removes arbitration with board and assumes the chipset controls the SPI flash bus entirely. config DISABLE_KEYBOARD_RESET_PIN bool help Instruct the SoC to not to reset based on the state of GPIO_21, KBDRST_L. menu "PSP Configuration Options" config AMDFW_CONFIG_FILE string "AMD PSP Firmware config file" default "src/soc/amd/glinda/fw.cfg" help Specify the path/location of AMD PSP Firmware config file. config PSP_DISABLE_POSTCODES bool "Disable PSP post codes" help Disables the output of port80 post codes from PSP. config PSP_POSTCODES_ON_ESPI bool "Use eSPI bus for PSP post codes" default y depends on !PSP_DISABLE_POSTCODES help Select to send PSP port80 post codes on eSPI bus. If not selected, PSP port80 codes will be sent on LPC bus. config PSP_LOAD_MP2_FW bool default n help Include the MP2 firmwares and configuration into the PSP build. If unsure, answer 'n' config PSP_UNLOCK_SECURE_DEBUG bool "Unlock secure debug" default y help Select this item to enable secure debug options in PSP. config HAVE_PSP_WHITELIST_FILE bool "Include a debug whitelist file in PSP build" default n help Support secured unlock prior to reset using a whitelisted serial number. This feature requires a signed whitelist image and bootloader from AMD. If unsure, answer 'n' config PSP_WHITELIST_FILE string "Debug whitelist file path" depends on HAVE_PSP_WHITELIST_FILE default "site-local/3rdparty/amd_blobs/glinda/PSP/wtl-mrg.sbin" config PERFORM_SPL_FUSING bool "Send SPL fuse command to PSP" default n help Send the Security Patch Level (SPL) fusing command to the PSP in order to update the minimum SPL version to be written to the SoC's fuse bits. This will prevent using any embedded firmware components with lower SPL version. If unsure, answer 'n' config SPL_TABLE_FILE string "SPL table file override" help Provide a mainboard-specific Security Patch Level (SPL) table file override. The SPL file is required to support PSP FW anti-rollback and needs to be created by AMD. The default SPL file specified in the SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule and applies to all boards that use the SoC without verstage on PSP. In the verstage on PSP case, a different SPL file is specific as an override via this Kconfig option. config HAVE_SPL_RW_AB_FILE bool "Have a separate mainboard-specific SPL file in RW A/B partitions" default n depends on VBOOT_SLOTS_RW_AB help Have separate mainboard-specific Security Patch Level (SPL) table file for the RW A/B FMAP partitions. config SPL_RW_AB_TABLE_FILE string "Separate SPL table file override for RW A/B partitions" config PSP_SOFTFUSE_BITS string "PSP Soft Fuse bits to enable" default "34 28 6" help Space separated list of Soft Fuse bits to enable. Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) Bit 7: Disable PSP postcodes on Renoir and newer chips only (Set by PSP_DISABLE_PORT80) Bit 15: PSP debug output destination: 0=SoC MMIO UART, 1=IO port 0x3F8 Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) See #55758 (NDA) for additional bit definitions. config PSP_VERSTAGE_FILE string "Specify the PSP_verstage file path" depends on VBOOT_STARTS_BEFORE_BOOTBLOCK default "\$(obj)/psp_verstage.bin" help Add psp_verstage file to the build & PSP Directory Table config PSP_VERSTAGE_SIGNING_TOKEN string "Specify the PSP_verstage Signature Token file path" depends on VBOOT_STARTS_BEFORE_BOOTBLOCK default "" help Add psp_verstage signature token to the build & PSP Directory Table endmenu config VBOOT select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH config VBOOT_STARTS_BEFORE_BOOTBLOCK def_bool n depends on VBOOT select ARCH_VERSTAGE_ARMV7 help Runs verstage on the PSP. Only available on certain ChromeOS branded parts from AMD. config VBOOT_HASH_BLOCK_SIZE hex default 0x9000 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK help Because the bulk of the time in psp_verstage to hash the RO cbfs is spent in the overhead of doing svc calls, increasing the hash block size significantly cuts the verstage hashing time as seen below. 4k takes 180ms 16k takes 44ms 32k takes 33.7ms 36k takes 32.5ms There's actually still room for an even bigger stack, but we've reached a point of diminishing returns. config CMOS_RECOVERY_BYTE hex default 0x51 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK help If the workbuf is not passed from the PSP to coreboot, set the recovery flag and reboot. The PSP will read this byte, mark the recovery request in VBNV, and reset the system into recovery mode. This is the byte before the default first byte used by VBNV (0x26 + 0x0E - 1) if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK config RWA_REGION_ONLY string default "apu/amdfw_a" help Add a space-delimited list of filenames that should only be in the RW-A section. config RWB_REGION_ONLY string default "apu/amdfw_b" help Add a space-delimited list of filenames that should only be in the RW-B section. endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK endif # SOC_AMD_GLINDA