# SPDX-License-Identifier: GPL-2.0-only

config SOC_AMD_CEZANNE
	bool
	help
	  AMD Cezanne support

if SOC_AMD_CEZANNE

config SOC_SPECIFIC_OPTIONS
	def_bool y
	select ARCH_BOOTBLOCK_X86_32
	select ARCH_VERSTAGE_X86_32
	select ARCH_ROMSTAGE_X86_32
	select ARCH_RAMSTAGE_X86_32
	select HAVE_CF9_RESET
	select IOAPIC
	select RESET_VECTOR_IN_RAM
	select SOC_AMD_COMMON
	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
	select SOC_AMD_COMMON_BLOCK_NONCAR
	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
	select SOC_AMD_COMMON_BLOCK_SMBUS
	select SOC_AMD_COMMON_BLOCK_SMI
	select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H

config EARLY_RESERVED_DRAM_BASE
	hex
	default 0x2000000
	help
	  This variable defines the base address of the DRAM which is reserved
	  for usage by coreboot in early stages (i.e. before ramstage is up).
	  This memory gets reserved in BIOS tables to ensure that the OS does
	  not use it, thus preventing corruption of OS memory in case of S3
	  resume.

config EARLYRAM_BSP_STACK_SIZE
	hex
	default 0x1000

config PSP_APOB_DRAM_ADDRESS
	hex
	default 0x2001000
	help
	  Location in DRAM where the PSP will copy the AGESA PSP Output
	  Block.

config PRERAM_CBMEM_CONSOLE_SIZE
	hex
	default 0x1600
	help
	  Increase this value if preram cbmem console is getting truncated

config C_ENV_BOOTBLOCK_SIZE
	hex
	default 0x10000
	help
	  Sets the size of the bootblock stage that should be loaded in DRAM.
	  This variable controls the DRAM allocation size in linker script
	  for bootblock stage.

config ROMSTAGE_ADDR
	hex
	default 0x2040000
	help
	  Sets the address in DRAM where romstage should be loaded.

config ROMSTAGE_SIZE
	hex
	default 0x80000
	help
	  Sets the size of DRAM allocation for romstage in linker script.

config FSP_M_ADDR
	hex
	default 0x20C0000
	help
	  Sets the address in DRAM where FSP-M should be loaded. cbfstool
	  performs relocation of FSP-M to this address.

config FSP_M_SIZE
	hex
	default 0x80000
	help
	  Sets the size of DRAM allocation for FSP-M in linker script.

config RAMBASE
	hex
	default 0x10000000

config CPU_ADDR_BITS
	int
	default 48

config MMCONF_BASE_ADDRESS
	hex
	default 0xF8000000

config MMCONF_BUS_NUMBER
	int
	default 64

endif # SOC_AMD_CEZANNE