uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS uses CONFIG_HAVE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT uses CONFIG_HAVE_HARD_RESET uses CONFIG_IRQ_SLOT_COUNT uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP uses CONFIG_FALLBACK_SIZE uses CONFIG_ROM_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_IMAGE_SIZE uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE uses CONFIG_STACK_SIZE uses CONFIG_HEAP_SIZE uses CONFIG_USE_OPTION_TABLE uses CONFIG_LB_CKS_RANGE_START uses CONFIG_LB_CKS_RANGE_END uses CONFIG_LB_CKS_LOC uses CONFIG_MAINBOARD uses CONFIG_MAINBOARD_PART_NUMBER uses CONFIG_MAINBOARD_VENDOR uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION uses CONFIG_RAMBASE uses CONFIG_TTYS0_BAUD uses CONFIG_TTYS0_BASE uses CONFIG_TTYS0_LCS uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB uses CONFIG_CROSS_COMPILE uses CC uses HOSTCC uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_HW_MEM_HOLE_SIZEK uses CONFIG_USE_DCACHE_RAM uses CONFIG_DCACHE_RAM_BASE uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR uses CONFIG_ENABLE_APIC_EXT_ID uses CONFIG_APIC_ID_OFFSET uses CONFIG_LIFT_BSP_APIC_ID ### ### Build options ### ## ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## default CONFIG_ROM_SIZE=524288 ## ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## default CONFIG_HAVE_PIRQ_TABLE=1 default CONFIG_IRQ_SLOT_COUNT=22 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## default CONFIG_HAVE_MP_TABLE=1 ## ## Build code to export a CMOS option table ## default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## default CONFIG_LB_CKS_RANGE_START=49 default CONFIG_LB_CKS_RANGE_END=122 default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support ## Only worry about 2 micro processors ## default CONFIG_SMP=1 default CONFIG_MAX_CPUS=8 default CONFIG_MAX_PHYSICAL_CPUS=4 default CONFIG_LOGICAL_CPUS=1 #1G memory hole default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## default CONFIG_USE_DCACHE_RAM=1 default CONFIG_DCACHE_RAM_BASE=0xcf000 default CONFIG_DCACHE_RAM_SIZE=0x1000 default CONFIG_USE_INIT=0 default CONFIG_ENABLE_APIC_EXT_ID=1 default CONFIG_APIC_ID_OFFSET=0x10 default CONFIG_LIFT_BSP_APIC_ID=0 ## ## Build code to setup a generic IOAPIC ## default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## default CONFIG_MAINBOARD_VENDOR="Tyan" default CONFIG_MAINBOARD_PART_NUMBER="s4880" default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880 ### ### coreboot layout values ### ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE ## ## Coreboot C code runs at this location in RAM ## default CONFIG_RAMBASE=0x00004000 ## ## Load the payload from the ROM ## default CONFIG_ROM_PAYLOAD = 1 ### ### Defaults of options that you may want to override in the target config file ### ## ## The default compiler ## default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" default HOSTCC="gcc" ## ## Disable the gdb stub by default ## default CONFIG_GDB_STUB=0 default CONFIG_USE_PRINTK_IN_CAR=1 ## ## The Serial Console ## # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate default CONFIG_TTYS0_BAUD=115200 #default CONFIG_TTYS0_BAUD=57600 #default CONFIG_TTYS0_BAUD=38400 #default CONFIG_TTYS0_BAUD=19200 #default CONFIG_TTYS0_BAUD=9600 #default CONFIG_TTYS0_BAUD=4800 #default CONFIG_TTYS0_BAUD=2400 #default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately ## CRIT 3 critical conditions ## ERR 4 error conditions ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational ## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # # CBFS # # default CONFIG_CBFS=1 end