include /config/nofailovercalculation.lb default CONFIG_ROM_PAYLOAD = 1 arch i386 end ## ## Build the objects we have code for in this directory. ## driver mainboard.o if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end if CONFIG_USE_INIT makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" end else makerule ./auto.inc depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end ## ## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end mainboardinit cpu/x86/32bit/entry32.inc if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds end if CONFIG_USE_INIT ldscript /cpu/amd/car/cache_as_ram.lds end ## ## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else mainboardinit cpu/x86/32bit/reset32.inc ldscript /cpu/x86/32bit/reset32.lds end ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds ## ## Setup Cache-As-Ram ## mainboardinit cpu/amd/car/cache_as_ram.inc ### ### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end ## ## Setup RAM ## if CONFIG_USE_INIT initobject auto.o else mainboardinit ./auto.inc end ## ## Include the secondary Configuration files ## config chip.h # sample config for tyan/s4880 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_940 device apic 0 on end end end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on end # LDT0 device pci 18.0 on end # LDT1 device pci 18.0 on # northbridge # devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on # chip drivers/lsi/53c1030 # device pci 4.0 on end # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end chip drivers/pci/onboard device pci 9.0 on end device pci 9.1 on end end end device pci 0.1 on end device pci 1.0 on end device pci 1.1 on end end chip southbridge/amd/amd8111 # this "device pci 0.0" is the parent the next one # PCI bridge device pci 0.0 on device pci 0.0 on end device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end chip drivers/pci/onboard device pci 6.0 on end register "rom_address" = "0xfff80000" end end device pci 1.0 on chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end device pnp 2e.6 off # CIR io 0x60 = 0x100 end device pnp 2e.7 off # GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 end end end device pci 1.1 on end device pci 1.2 on end device pci 1.3 on end device pci 1.5 off end device pci 1.6 off end register "ide0_enable" = "1" register "ide1_enable" = "1" end end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end end #pci_domain end