##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
	default ROM_SECTION_SIZE   = FAILOVER_SIZE
	default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
else
    if USE_FALLBACK_IMAGE
	default ROM_SECTION_SIZE   = FALLBACK_SIZE
	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
    else
	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
	default ROM_SECTION_OFFSET = 0
    end
end

##
## Compute the start location and size size of
## The coreboot bootloader.
##
default PAYLOAD_SIZE	     = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)

##
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536

if USE_FAILOVER_IMAGE
	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
else
	if USE_FALLBACK_IMAGE
		default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
	else
		default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
	end
end

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o

if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o

if USE_DCACHE_RAM

if CONFIG_USE_INIT
	makerule ./auto.o
		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
		action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
	end
else
	makerule ./auto.inc
		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
		action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -g -dA -fverbose-asm -c -S -o $@"
		action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
	end
end

else
	##
	## Romcc output
	##
	makerule ./failover.E
		depends "$(MAINBOARD)/failover.c ../romcc"
		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
	end

	makerule ./failover.inc
		depends "$(MAINBOARD)/failover.c ../romcc"
		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
	end

	makerule ./auto.E
		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
		action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
	end

	makerule ./auto.inc
		depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
		action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
	end

end

##
## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
	if USE_FAILOVER_IMAGE
		mainboardinit cpu/x86/16bit/entry16.inc
		ldscript /cpu/x86/16bit/entry16.lds
	end
else
	if USE_FALLBACK_IMAGE
		mainboardinit cpu/x86/16bit/entry16.inc
		ldscript /cpu/x86/16bit/entry16.lds
	end
end

mainboardinit cpu/x86/32bit/entry32.inc

if USE_DCACHE_RAM
	if CONFIG_USE_INIT
		ldscript /cpu/x86/32bit/entry32.lds
	end

	if CONFIG_USE_INIT
		ldscript /cpu/amd/car/cache_as_ram.lds
	end
end

##
## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
    if USE_FAILOVER_IMAGE
	mainboardinit cpu/x86/16bit/reset16.inc
	ldscript /cpu/x86/16bit/reset16.lds
    else
	mainboardinit cpu/x86/32bit/reset32.inc
	ldscript /cpu/x86/32bit/reset32.lds
    end
else
    if USE_FALLBACK_IMAGE
	mainboardinit cpu/x86/16bit/reset16.inc
	ldscript /cpu/x86/16bit/reset16.lds
    else
	mainboardinit cpu/x86/32bit/reset32.inc
	ldscript /cpu/x86/32bit/reset32.lds
    end
end

if USE_DCACHE_RAM
else
	### Should this be in the northbridge code?
	mainboardinit arch/i386/lib/cpu_reset.inc
end

##
## Include an id string (For safe flashing)
##
mainboardinit southbridge/nvidia/ck804/id.inc
ldscript /southbridge/nvidia/ck804/id.lds

##
## ROMSTRAP table for CK804
##
if HAVE_FAILOVER_BOOT
	if USE_FAILOVER_IMAGE
		mainboardinit southbridge/nvidia/ck804/romstrap.inc
		ldscript /southbridge/nvidia/ck804/romstrap.lds
	end
else
	if USE_FALLBACK_IMAGE
		mainboardinit southbridge/nvidia/ck804/romstrap.inc
		ldscript /southbridge/nvidia/ck804/romstrap.lds
	end
end

if USE_DCACHE_RAM
	##
	## Setup Cache-As-Ram
	##
	mainboardinit cpu/amd/car/cache_as_ram.inc
end

###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if HAVE_FAILOVER_BOOT
	if USE_FAILOVER_IMAGE
		if USE_DCACHE_RAM
			ldscript /arch/i386/lib/failover_failover.lds
		end
	end
else
	if USE_FALLBACK_IMAGE
		if USE_DCACHE_RAM
			ldscript /arch/i386/lib/failover.lds
		else
			mainboardinit ./failover.inc
		end
	end
end

##
## Setup RAM
##
if USE_DCACHE_RAM

	if CONFIG_USE_INIT
		initobject auto.o
	else
		mainboardinit ./auto.inc
	end

else
	# ROMCC
	mainboardinit cpu/x86/fpu/enable_fpu.inc
	mainboardinit cpu/x86/mmx/enable_mmx.inc
	mainboardinit cpu/x86/sse/enable_sse.inc
	mainboardinit ./auto.inc
	mainboardinit cpu/x86/sse/disable_sse.inc
	mainboardinit cpu/x86/mmx/disable_mmx.inc

end

##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
	config chip.h
end

# sample config for tyan/s2895
chip northbridge/amd/amdk8/root_complex
	device apic_cluster 0 on
		chip cpu/amd/socket_940
			device apic 0 on end
		end
	end
	device pci_domain 0 on
		chip northbridge/amd/amdk8 #mc0
			device pci 18.0 on #  northbridge
				#  devices on link 0, link 0 == LDT 0
				chip southbridge/nvidia/ck804
					device pci 0.0 on end   # HT
					device pci 1.0 on # LPC
						chip superio/smsc/lpc47b397
							device pnp 2e.0 on #  Floppy
								io 0x60 = 0x3f0
								irq 0x70 = 6
								drq 0x74 = 2
							end
							device pnp 2e.3 off #  Parallel Port
								io 0x60 = 0x378
								irq 0x70 = 7
							end
							device pnp 2e.4 on #  Com1
								io 0x60 = 0x3f8
								irq 0x70 = 4
							end
							device pnp 2e.5 off #  Com2
								io 0x60 = 0x2f8
								irq 0x70 = 3
							end
							device pnp 2e.7 on #  Keyboard
								io 0x60 = 0x60
								io 0x62 = 0x64
								irq 0x70 = 1
								irq 0x72 = 12
							end
							device pnp 2e.8 on # HW Monitor
								io 0x60 = 0x290
								chip drivers/generic/generic # LM95221 CPU temp
									device i2c 2b on end
								end
								chip drivers/generic/generic # EMCT03
									device i2c 54 on end
								end
							end
							device	pnp 2e.a on #  RT
								io 0x60 = 0x400
							end
						end
					end
					device pci 1.1 on # SM 0
						chip drivers/generic/generic #dimm 0-0-0
							device i2c 50 on end
						end
						chip drivers/generic/generic #dimm 0-0-1
							device i2c 51 on end
						end
						chip drivers/generic/generic #dimm 0-1-0
							device i2c 52 on end
						end
						chip drivers/generic/generic #dimm 0-1-1
							device i2c 53 on end
						end
						chip drivers/generic/generic #dimm 1-0-0
							device i2c 54 on end
						end
						chip drivers/generic/generic #dimm 1-0-1
							device i2c 55 on end
						end
						chip drivers/generic/generic #dimm 1-1-0
							device i2c 56 on end
						end
						chip drivers/generic/generic #dimm 1-1-1
							device i2c 57 on end
						end
					end # SM
					device pci 1.1 on # SM 1
						chip drivers/generic/generic #MAC EEPROM
							device i2c 51 on end
						end

					end # SM
					device pci 2.0 on end # USB 1.1
					device pci 2.1 on end # USB 2
					device pci 4.0 on end # ACI
					device pci 4.1 off end # MCI
					device pci 6.0 on end # IDE
					device pci 7.0 on end # SATA 1
					device pci 8.0 on end # SATA 0
					device pci 9.0 on end # PCI
					device pci a.0 on end # NIC
		       			device pci b.0 off end # PCI E 3
					device pci c.0 off end # PCI E 2
					device pci d.0 off end # PCI E 1
					device pci e.0 on end # PCI E 0
					register "ide0_enable" = "1"
					register "ide1_enable" = "1"
					register "sata0_enable" = "1"
					register "sata1_enable" = "1"
#					register "nic_rom_address" = "0xfff80000" # 64k
#					register "raid_rom_address" = "0xfff90000"
					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
					register "mac_eeprom_addr" = "0x51"
				end
			end #  device pci 18.0
			device pci 18.0 on end # Link 1
			device pci 18.0 on
			#  devices on link 2, link 2 == LDT 2
				chip southbridge/amd/amd8131
					# the on/off keyword is mandatory
					device pci 0.0 on end
					device pci 0.1 on end
					device pci 1.0 on
						chip drivers/pci/onboard
							device pci 6.0 on end # lsi scsi
							device pci 6.1 on end
						end
					end
					device pci 1.1 on end
				end
			end # device pci 18.0
			device pci 18.1 on end
			device pci 18.2 on end
			device pci 18.3 on end
		end #mc0

		chip northbridge/amd/amdk8
			device pci 19.0 on #  northbridge
				#  devices on link 0, link 0 == LDT 0
				chip southbridge/nvidia/ck804
					device pci 0.0 on end   # HT
					device pci 1.0 on end   # LPC
					device pci 1.1 off end # SM
					device pci 2.0 off end # USB 1.1
					device pci 2.1 off end # USB 2
					device pci 4.0 off end # ACI
					device pci 4.1 off end # MCI
					device pci 6.0 off end # IDE
					device pci 7.0 off end # SATA 1
					device pci 8.0 off end # SATA 0
					device pci 9.0 off end # PCI
					device pci a.0 on end # NIC
					device pci b.0 off end # PCI E 3
					device pci c.0 off end # PCI E 2
					device pci d.0 off end # PCI E 1
					device pci e.0 on end # PCI E 0
#					register "nic_rom_address" = "0xfff80000" # 64k
					register "mac_eeprom_smbus" = "3"
					register "mac_eeprom_addr" = "0x51"
				end
			end #  device pci 19.0

			device pci 19.0 on end
			device pci 19.0 on end
			device pci 19.1 on end
			device pci 19.2 on end
			device pci 19.3 on end
		end
	end # PCI domain

#	chip drivers/generic/debug
#		device pnp 0.0 off end # chip name
#		device pnp 0.1 off end # pci_regs_all
#		device pnp 0.2 off end # mem
#		device pnp 0.3 off end # cpuid
#		device pnp 0.4 on  end # smbus_regs_all
#		device pnp 0.5 off end # dual core msr
#		device pnp 0.6 off end # cache size
#		device pnp 0.7 off end # tsc
#	end
end # root_complex