uses HAVE_MP_TABLE
uses CONFIG_CBFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses SERIAL_CPU_INIT
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN

uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT

## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes 
default ROM_SIZE=524288

#1M bytes
#default ROM_SIZE=1048576


##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
default FALLBACK_SIZE=131072

###
### Build options
###

##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1

##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1

## Delay timer options
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1

##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=15

##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=1

##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1

##
## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
default LB_CKS_LOC=123

##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1

default SERIAL_CPU_INIT=0

#BTEXT Console
#default CONFIG_CONSOLE_BTEXT=1

#VGA Console
#default CONFIG_CONSOLE_VGA=1
#default CONFIG_PCI_ROM_RUN=1

##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
#default DCACHE_RAM_BASE=0xF2000000
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
#default CONFIG_USE_INIT=1


##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1

##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="s2735"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735

###
### coreboot layout values
###

## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536

##
## Use a small 8K stack
##
default STACK_SIZE=0x2000

##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000

##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE

##
## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00004000

##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD = 1

###
### Defaults of options that you may want to override in the target config file
### 

##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"

##
## Disable the gdb stub by default
## 
default CONFIG_GDB_STUB=0

##
## The Serial Console
##

# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1

## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200

# Select the serial console base port
default TTYS0_BASE=0x3f8

# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3

##
### Select the coreboot loglevel
##
## EMERG      1   system is unusable               
## ALERT      2   action must be taken immediately 
## CRIT       3   critical conditions              
## ERR        4   error conditions                 
## WARNING    5   warning conditions               
## NOTICE     6   normal but significant condition 
## INFO       7   informational                    
## DEBUG      8   debug-level messages             
## SPEW       9   Way too many details             

## Request this level of debugging output
default  DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default  MAXIMUM_CONSOLE_LOGLEVEL=8

##
## Select power on after power fail setting
default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"

### End Options.lb
#
# CBFS
#
#
default CONFIG_CBFS=0
end