; bdiGDB configuration file for briQ (http://www.totalimpact.com) ; --------------------------------------------------------------- ; ; NOTE: As of June 2004, you will need to install a pull-down ; on the COP/JTAG QACK line. Without this, the BDI2000 ; is not able to halt the CPU ; (http://www.ultsol.com/faq-P210.htm) ; [INIT] ; init core register WREG MSR 0x00000000 ;clear MSR ; ; init CPC710 ; WM32 0xFF000010 0xF0000000 ; RSTR WM32 0xFF001020 0x00000000 ; SIOC WM32 0xFF001000 0x00780000 ; UCTL (resID=7|TBE) WM32 0xFF001030 0x00000000 ; ABCNTL WM32 0xFF001040 0x00000000 ; SRST WM32 0xFF001050 0x00000000 ; ERRC WM32 0xFF001060 0x00000000 ; SESR WM32 0xFF001070 0x00000000 ; SEAR WM32 0xFF001100 0x000000E0 ; PGCHP (PReP|ARTRY|750|SYS_TEA) WM32 0xFF001130 0x40000000 ; GPDIR WM32 0xFF001150 0x40000000 ; GPOUT WM32 0xFF001160 0x709C2508 ; ATAS WM32 0xFF001170 0x00000000 ; AVDG WM32 0xFF001220 0x00000000 ; MESR WM32 0xFF001230 0x00000000 ; MEAR WM32 0xFF001210 0x00000000 ; MWPR WM32 0xFF001120 0x00000000 ; RGBAN1 ; ; init memory - this assumes 2 x 512MB DIMMs ; WM32 0xFF001300 0x80000080 ; MCER0 WM32 0xFF001310 0x82000080 ; MCER1 WM32 0xFF001320 0x00000000 ; MCER2 WM32 0xFF001330 0x00000000 ; MCER3 WM32 0xFF001340 0x00000000 ; MCER4 WM32 0xFF001350 0x00000000 ; MCER5 WM32 0xFF001200 0xD2B06000 ; MCCR DELAY 1000 ; ; enable pci ; WM32 0xFF00000C 0x80000002 ; CNFR WM32 0xFF200018 0xFF500000 ; PCIBAR WM32 0xFF201000 0x80000000 ; PCIENB WM32 0xFF00000C 0x00000000 ; CNFR ; ; config pci ; WM32 0xFF5F8000 0x06000080 WM16 0xFF5F8010 0xFFFF WM32 0xFF5F8000 0x40000080 WM16 0xFF5F8010 0x0000 WM32 0xFF5F6120 0x40000000 ; PCIDG WM32 0xFF5F7800 0x00000000 ; PIBAR WM32 0xFF5F7810 0x00000000 ; PMBAR WM32 0xFF5F7F20 0xA000C000 ; PR WM32 0xFF5F7F30 0xFC000000 ; ACR WM32 0xFF5F7F40 0xF8000000 ; MSIZE WM32 0xFF5F7F60 0xF8000000 ; IOSIZE WM32 0xFF5F7F80 0xC0000000 ; SMBAR WM32 0xFF5F7FC0 0x80000000 ; SIBAR WM32 0xFF5F8100 0x00000080 ; PSSIZE WM32 0xFF5F8120 0x00000000 ; BARPS WM32 0xFF5F8140 0x00000080 ; PSBAR WM32 0xFF5F8200 0x00000000 ; BPMDLK WM32 0xFF5F8210 0x00000000 ; TPMDLK WM32 0xFF5F8220 0x00000000 ; BIODLK WM32 0xFF5F8230 0x00000000 ; TIODLK WM32 0xFF5F8000 0x04000080 WM16 0xFF5F8010 0xA7FD WM32 0xFF5F7EF0 0xFC000000 ; CRR ; ; VFD - output the sequence '01234' to show ; something is happening ; ;WM8 0x80000390 0x38 ;WM8 0x80000390 0x01 ;WM8 0x80000390 0x0C ;WM8 0x80000390 0x06 ;WM8 0x80000390 0x02 ;DELAY 100 ;WM8 0x80000391 0x30 ;DELAY 100 ;WM8 0x80000391 0x31 ;DELAY 100 ;WM8 0x80000391 0x32 ;DELAY 100 ;WM8 0x80000391 0x33 ;DELAY 100 ;WM8 0x80000391 0x34 ; ; UART - output the sequence '01234' to show ; something is happening ; WM8 0x800003F9 0 WM8 0x800003FA 1 WM8 0x800003FB 0x83 WM8 0x800003F8 4 ; 115200 WM8 0x800003F9 0 WM8 0x800003FB 0x3 DELAY 100 WM8 0x800003F8 0x30 DELAY 100 WM8 0x800003F8 0x31 DELAY 100 WM8 0x800003F8 0x32 DELAY 100 WM8 0x800003F8 0x33 DELAY 100 WM8 0x800003F8 0x34 ; ; define maximal transfer size ;TSZ1 0xFF800000 0xFFFFFFFF ;ROM space (only for PCI boot ROM) TSZ4 0xFF800000 0xFFFFFFFF ;ROM space (only for Local bus flash) [TARGET] CPUTYPE 7400 ;the CPU type (603EV,750,8240,8260,7400) JTAGCLOCK 0 ;use 16 MHz JTAG clock WORKSPACE 0x00000000 ;workspace in target RAM for data cache flush BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY) BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE TRACE ;TRACE or HWBP, HWPB uses a hardware breakpoint ;VECTOR CATCH ;catch unhandled exceptions DCACHE FLUSH ;data cache flushing (FLUSH | NOFLUSH) ;PARITY ON ;enable data parity generation ;MEMDELAY 4000 ;additional memory access delay ;REGLIST STD ;select register to transfer to GDB ;L2PM 0x00100000 0x80000 ;L2 privat memory BOOTADDR 0xfff00100 STARTUP RESET [HOST] FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset DEBUGPORT 2001 [FLASH] ; Am29LV800BB on local processor bus (RCS0) ; set PPMC7410 switch SW2-1 OFF => ROM on Local bus ; enable flash write in PICR1 (see INIT part) ; set maximal transfer size to 4 bytes (see INIT part) CHIPTYPE AM29F ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) CHIPSIZE 0x100000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000) BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64) ;WORKSPACE 0x00000000 ;workspace in SDRAM FILE linuxbios.rom FORMAT ELF ERASE 0xFFF00000 ;erase sector 0 of flash ERASE 0xFFF10000 ;erase sector 1 of flash ERASE 0xFFF20000 ;erase sector 2 of flash ERASE 0xFFF30000 ;erase sector 3 of flash ERASE 0xFFF40000 ;erase sector 4 of flash ERASE 0xFFF50000 ;erase sector 5 of flash ERASE 0xFFF60000 ;erase sector 6 of flash ERASE 0xFFF70000 ;erase sector 7 of flash ;ERASE 0xFFF80000 ;erase sector 8 of flash ;ERASE 0xFFF90000 ;erase sector 9 of flash ;ERASE 0xFFFA0000 ;erase sector 10 of flash ;ERASE 0xFFFB0000 ;erase sector 11 of flash ;ERASE 0xFFFC0000 ;erase sector 12 of flash ;ERASE 0xFFFD0000 ;erase sector 13 of flash ;ERASE 0xFFFE0000 ;erase sector 14 of flash ;ERASE 0xFFFF0000 ;erase sector 15 of flash [REGS] ;DMM1 0xFC000000 ;Embedded utility memory base address ;IMM1 0xFEC00000 0xFEE00000 ;configuration registers at byte offset 0 ;IMM2 0xFEC00000 0xFEE00001 ;configuration registers at byte offset 1 ;IMM3 0xFEC00000 0xFEE00002 ;configuration registers at byte offset 2 ;IMM4 0xFEC00000 0xFEE00003 ;configuration registers at byte offset 3 FILE cpc700.def