##
## Config file for the Total Impact briQ
##

uses TTYS0_DIV
uses TTYS0_BASE
uses CONFIG_BRIQ_750FX
uses CONFIG_BRIQ_7400
uses ISA_IO_BASE
uses ISA_MEM_BASE
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
uses _IO_BASE

##
## Set memory map
##
default ISA_IO_BASE=0x80000000
default ISA_MEM_BASE=0xc0000000
default PCIC0_CFGADDR=0xff5f8000
default PCIC0_CFGDATA=0xff5f8010
default _IO_BASE=ISA_IO_BASE

##
## The briQ uses weird clocking, 4 = 115200
##
default TTYS0_DIV=4
##
## Set UART base address
##
default TTYS0_BASE=0x3f8

##
## Early board initialization, called from ppc_main()
##
initobject init.o
initobject clock.o

##
## Stage 2 timer support
##
object clock.o

arch ppc end

if CONFIG_BRIQ_750FX
	cpu ppc/ppc7xx end
end
if CONFIG_BRIQ_7400
	cpu ppc/mpc74xx end
end

##
## Include the secondary Configuration files 
##
northbridge ibm/cpc710 end
southbridge winbond/w83c553 end

##
## Build the objects we have code for in this directory.
##

addaction linuxbios.a "$(CROSS_COMPILE)ranlib linuxbios.a"