default ROM_SIZE = 128 * 1024 
default FALLBACK_SIZE = 0x10000

## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE = 32 * 1024
include /config/nofailovercalculation.lb

##
## Set all of the defaults for an x86 architecture
##

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
# object reset.o

##
## Romcc output
##
makerule ./failover.E
	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end

makerule ./failover.inc
	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end

makerule ./auto.E 
	depends	"$(MAINBOARD)/auto.c option_table.h ../romcc" 
	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc 
	depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end

##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds

##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE 
	mainboardinit cpu/x86/16bit/reset16.inc 
	ldscript /cpu/x86/16bit/reset16.lds 
else
	mainboardinit cpu/x86/32bit/reset32.inc 
	ldscript /cpu/x86/32bit/reset32.lds 
end

### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc

##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds

###
### This is the early phase of coreboot startup 
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
	ldscript /arch/i386/lib/failover.lds 
	mainboardinit ./failover.inc
end


# VGA console
#if CONFIG_CONSOLE_VGA
#	default CONFIG_PCI_ROM_RUN=1
#end
###
### O.k. We aren't just an intermediary anymore!
###

##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit ./auto.inc

##
## Include the secondary Configuration files 
##
dir /pc80
dir /devices
config chip.h

chip cpu/amd/sc520
	device pci_domain 0 on 
		device pci 0.0 on end
	
#		chip drivers/pci/onboard
#			device pci 12.0 on end # enet
#		end
#		chip drivers/pci/onboard
#			device pci 14.0 on end # 69000
#			register "rom_address" = "0x2000000"
#		end
#		register "com1" = "{1}"
#		register "com1" = "{1, 0, 0x3f8, 4}"
	end

end