# SPDX-License-Identifier: GPL-2.0-only

chip soc/intel/cannonlake
	# Lock Down
	register "common_soc_config" = "{
		.i2c[0] = {
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 80,
			.fall_time_ns = 110,
		},
	}"

# CPU (soc/intel/cannonlake/cpu.c)
	# Power limit
	register "power_limits_config" = "{
		.tdp_pl1_override = 20,
		.tdp_pl2_override = 30,
	}"

	# Enable Enhanced Intel SpeedStep
	register "eist_enable" = "1"

# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
	register "SaGv" = "SaGv_Enabled"
	register "enable_c6dram" = "1"

# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
	# Serial I/O
	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0] = PchSerialIoPci,
		[PchSerialIoIndexUART2] = PchSerialIoPci,
	}"

	# Misc
	register "AcousticNoiseMitigation" = "1"

	# Power
	register "PchPmSlpS3MinAssert" = "3"	# 50ms
	register "PchPmSlpS4MinAssert" = "1"	# 1s
	register "PchPmSlpSusMinAssert" = "2"	# 500ms
	register "PchPmSlpAMinAssert" = "4"	# 2s

	# Thermal
	register "tcc_offset" = "12"

	# Serial IRQ Continuous
	register "serirq_mode" = "SERIRQ_CONTINUOUS"

# PM Util (soc/intel/cannonlake/pmutil.c)
	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "gpe0_dw0" = "PMC_GPP_C"
	register "gpe0_dw1" = "PMC_GPP_D"
	register "gpe0_dw2" = "PMC_GPP_E"

# Actual device tree
	device domain 0 on
		device ref igpu		on
			register "gfx" = "GMA_STATIC_DISPLAYS(0)"
		end
		device ref dptf		on
			register "Device4Enable" = "1"
		end
		device ref thermal	on  end
		device ref xhci		on
			register "usb2_ports" = "{
				[0] = USB2_PORT_MID(OC_SKIP),		/* USB-A */
				[1] = USB2_PORT_MID(OC_SKIP),		/* 3G / LTE */
				[2] = USB2_PORT_TYPE_C(OC_SKIP),	/* USB-C */
				[3] = USB2_PORT_MID(OC_SKIP),		/* USB-A */
				[6] = USB2_PORT_MAX(OC_SKIP),		/* Camera */
				[9] = USB2_PORT_MID(OC_SKIP),		/* Bluetooth */
			}"
			register "usb3_ports" = "{
				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* USB-A */
				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* 4G on galp3-c, NC on darp5 */
				[2] = USB3_PORT_DEFAULT(OC_SKIP),	/* USB-C */
				[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* USB-A */
				[4] = USB3_PORT_EMPTY,			/* Used by TBT */
				[5] = USB3_PORT_EMPTY,			/* Used by TBT */
			}"
		end
		device ref cnvi_wifi	on
			chip drivers/wifi/generic
				register "wake" = "PME_B0_EN_BIT"
				device generic 0 on end
			end
		end
		device ref i2c0		on	end
		device ref sata		on
			register "SataPortsEnable" = "{
				[0] = 1,
				[2] = 1,
			}"
		end
		device ref uart2	on	end
		device ref pcie_rp1	on	end
		device ref pcie_rp5	on
			# PCI Express Root port #5 x4, Clock 4 (TBT)
			register "PcieRpEnable[4]" = "1"
			register "PcieRpLtrEnable[4]" = "1"
			register "PcieRpHotPlug[4]" = "1"
			register "PcieClkSrcUsage[4]" = "4"
			register "PcieClkSrcClkReq[4]" = "4"
		end
		device ref pcie_rp9	on
			# PCI Express Root port #9 x1, Clock 3 (LAN)
			register "PcieRpEnable[8]" = "1"
			register "PcieRpLtrEnable[8]" = "1"
			register "PcieClkSrcUsage[3]" = "8"
			register "PcieClkSrcClkReq[3]" = "3"
		end
		device ref pcie_rp10	on
			# PCI Express Root port #10 x1, Clock 2 (WLAN)
			register "PcieRpEnable[9]" = "1"
			register "PcieRpLtrEnable[9]" = "0"
			register "PcieClkSrcUsage[2]" = "9"
			register "PcieClkSrcClkReq[2]" = "2"
		end
		device ref pcie_rp13	on
			# PCI Express Root port #13 x4, Clock 5 (NVMe)
			register "PcieRpEnable[12]" = "1"
			register "PcieRpLtrEnable[12]" = "1"
			register "PcieClkSrcUsage[5]" = "12"
			register "PcieClkSrcClkReq[5]" = "5"
		end
		device ref lpc_espi	on
			register "gen1_dec" = "0x000c0081"
			register "gen2_dec" = "0x00040069"
			register "gen3_dec" = "0x00fc0e01"
			register "gen4_dec" = "0x00fc0f01"
			chip drivers/pc80/tpm
				device pnp 0c31.0 on end
			end
		end
		device ref hda		on
			register "PchHdaAudioLinkHda" = "1"
			register "PchHdaAudioLinkDmic0" = "1"
			register "PchHdaAudioLinkDmic1" = "1"
		end
		device ref smbus	on	end
	end
end