# SPDX-License-Identifier: GPL-2.0-only chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 51, }" register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 51, }" # GPE configuration register "pmc_gpe0_dw0" = "PMC_GPP_A" register "pmc_gpe0_dw1" = "PMC_GPP_R" register "pmc_gpe0_dw2" = "PMC_GPD" device domain 0 on subsystemid 0x1558 0x4018 inherit device ref peg on # PCIe PEG0 x4, Clock 0 (SSD1) register "PcieClkSrcUsage[0]" = "0x40" register "PcieClkSrcClkReq[0]" = "0" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 register "srcclk_pin" = "0" # SSD1_CLKREQ# device generic 0 on end end end device ref north_xhci on # J_TYPEC2 register "UsbTcPortEn" = "1" register "TcssXhciEn" = "1" chip drivers/usb/acpi device ref tcss_root_hub on chip drivers/usb/acpi register "desc" = ""USB3 J_TYPEC2"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(1, 1)" device ref tcss_usb3_port1 on end end end end end device ref tbt_dma0 on # J_TYPEC2 chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" use tcss_usb3_port1 as dfp[0].typec_port device generic 0 on end end end device ref south_xhci on register "usb2_ports" = "{ [0] = USB2_PORT_MID(OC_SKIP), /* J_USB3_2 */ [1] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC1 */ [2] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */ [4] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */ [5] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC2 */ [6] = USB2_PORT_MID(OC_SKIP), /* Camera */ [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ }" register "usb3_ports" = "{ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_2 */ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH0 */ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH1 */ }" # ACPI chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""USB2 J_USB3_2"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(1, 2)" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 J_TYPEC1"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 J_USB3_1"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(2, 2)" device ref usb2_port3 on end end chip drivers/usb/acpi register "desc" = ""USB2 Fingerprint"" register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port5 on end end chip drivers/usb/acpi register "desc" = ""USB2 J_TYPEC2"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(1, 1)" device ref usb2_port6 on end end chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port7 on end end chip drivers/usb/acpi register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port10 on end end chip drivers/usb/acpi register "desc" = ""USB3 J_USB3_2"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(1, 2)" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 J_TYPEC1 CH0"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 J_USB3_1"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(2, 2)" device ref usb3_port3 on end end chip drivers/usb/acpi register "desc" = ""USB3 J_TYPEC1 CH1"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb3_port4 on end end end end end device ref i2c2 on # TODO: Pantone ROM? register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" end device ref pcie_rp5 on # PCIe root port #5 x4, Clock 2 (NVIDIA GPU) register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[2]" = "4" register "PcieClkSrcClkReq[2]" = "2" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH register "enable_delay_ms" = "16" register "enable_off_delay_ms" = "4" register "reset_delay_ms" = "10" register "reset_off_delay_ms" = "4" register "srcclk_pin" = "2" # PEG_CLKREQ# device generic 0 on end end end device ref pcie_rp9 on # PCIe root port #9 x1, Clock 3 (CARD) register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[3]" = "8" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp10 on # PCIe root port #10 x1, Clock 4 (GLAN) register "PcieRpLtrEnable[9]" = "1" register "PcieClkSrcUsage[4]" = "9" register "PcieClkSrcClkReq[4]" = "4" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # GPIO_LANRTD3 register "srcclk_pin" = "4" # LAN_CLKREQ# device generic 0 on end end end device ref pcie_rp11 on # PCIe root port #11 x1, Clock 1 (WLAN) register "PcieRpLtrEnable[10]" = "1" register "PcieClkSrcUsage[1]" = "10" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[10]" = "1" end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux device generic 0 on chip drivers/intel/pmc_mux/conn # J_TYPEC2 use usb2_port6 as usb2_port use tcss_usb3_port1 as usb3_port # SBU & HSL follow CC device generic 0 alias conn0 on end end end end end end end