chip soc/intel/tigerlake
	register "common_soc_config" = "{
		// Touchpad I2C bus
		.i2c[0] = {
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 80,
			.fall_time_ns = 110,
		},
	}"

# ACPI (soc/intel/tigerlake/acpi.c)
	# Enable Enhanced Intel SpeedStep
	register "eist_enable" = "1"

# CPU (soc/intel/tigerlake/cpu.c)
	# Power limits
	register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{
		.tdp_pl1_override = 45,
		.tdp_pl2_override = 90,
	}"
	register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{
		.tdp_pl1_override = 45,
		.tdp_pl2_override = 90,
	}"

# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
	# Enable C6 DRAM
	register "enable_c6dram" = "1"

# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
	# Acoustic settings
	register "AcousticNoiseMitigation" = "1"
	register "SlowSlewRate" = "SLEW_FAST_8"
	register "FastPkgCRampDisable" = "1"

	# FIVR configuration
	#   Read EXT_RAIL_CONFIG to determine bitmaps
	#     sudo devmem2 0xfe0011b8
	#     0x0
	#   Read EXT_V1P05_VR_CONFIG
	#     sudo devmem2 0xfe0011c0
	#     0x1a42000
	#   Read EXT_VNN_VR_CONFIG0
	#     sudo devmem2 0xfe0011c4
	#     0x1a42000
	# TODO: v1p05 voltage and vnn icc max?
	register "ext_fivr_settings" = "{
		.configure_ext_fivr = 1,
		.v1p05_enable_bitmap = 0,
		.vnn_enable_bitmap = 0,
		.v1p05_supported_voltage_bitmap = 0,
		.vnn_supported_voltage_bitmap = 0,
		.v1p05_icc_max_ma = 500,
		.vnn_sx_voltage_mv = 1050,
	}"

	# Read LPM_EN, make sure to invert the bits
	# sudo devmem2 0xfe001c78
	# 0x9
	register "LpmStateDisableMask" = "
		LPM_S0i2_1 |
		LPM_S0i2_2 |
		LPM_S0i3_1 |
		LPM_S0i3_2 |
		LPM_S0i3_3 |
		LPM_S0i3_4
	"

	# Thermal
	register "tcc_offset" = "10"

	# Enable CNVi BT
	register "CnviBtCore" = "true"

# PM Util (soc/intel/tigerlake/pmutil.c)
	# GPE configuration
	register "pmc_gpe0_dw0" = "PMC_GPP_R"
	register "pmc_gpe0_dw1" = "PMC_GPP_B"
	register "pmc_gpe0_dw2" = "PMC_GPP_D"

# Actual device tree
	device cpu_cluster 0 on
		device lapic 0 on end
	end

	device domain 0 on
		subsystemid 0x1558 0x65f1 inherit

		#From CPU EDS(575683)
		device ref system_agent on end
		device ref peg1 on
			# PCIe PEG1 x16, Clock 9 (DGPU)
			register "PcieClkSrcUsage[9]" = "0x41"
			register "PcieClkSrcClkReq[9]" = "9"
			chip soc/intel/common/block/pcie/rtd3
				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
				register "enable_delay_ms" = "16"
				register "enable_off_delay_ms" = "4"
				register "reset_delay_ms" = "10"
				register "reset_off_delay_ms" = "4"
				# TODO: Support disable/enable CPU RP clock
				register "srcclk_pin" = "-1" # PEG_CLKREQ#
				device generic 0 on end
			end
		end
		device ref igpu on
			# DDIA is eDP
			register "DdiPortAConfig" = "1"
			register "DdiPortAHpd" = "1"
			register "DdiPortADdc" = "0"
		end
		device ref dptf on end
		device ref peg0 on
			# PCIe PEG0 x4, Clock 7 (SSD1)
			register "PcieClkSrcUsage[7]" = "0x40"
			register "PcieClkSrcClkReq[7]" = "7"
		end
		device ref tbt_pcie_rp0 on end # TYPEC1
		device ref gna on end
		device ref north_xhci on # TYPEC1
			register "TcssXhciEn" = "1"
		end
		device ref tbt_dma0 on end # TYPEC1

		# From PCH EDS(615985)
		device ref south_xhci on
			# USB2
			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key
			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
			register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1
			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
			# USB3
			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
		end
		device ref shared_ram on end
		device ref cnvi_wifi on
			chip drivers/wifi/generic
				register "wake" = "GPE0_PME_B0"
				device generic 0 on end
			end
		end
		device ref i2c0 on
			# Touchpad I2C bus
			register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
			chip drivers/i2c/hid
				register "generic.hid" = ""SYNA1202""
				register "generic.desc" = ""Synaptics Touchpad""
				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_R12)"
				register "generic.probed" = "1"
				register "hid_desc_reg_offset" = "0x20"
				device i2c 2c on end
			end
		end
		device ref heci1 on end
		device ref uart2 on
			# Debug console
			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
		end
		device ref sata on
			register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)
		end
		device ref pcie_rp5 on
			# PCIe root port #5 x1, Clock 8 (GLAN)
			register "PcieRpEnable[4]" = "1"
			register "PcieRpLtrEnable[4]" = "1"
			register "PcieClkSrcUsage[8]" = "4"
			register "PcieClkSrcClkReq[8]" = "8"
		end
		device ref pcie_rp6 on
			# PCIe root port #6 x1, Clock 10 (CARD)
			register "PcieRpEnable[5]" = "1"
			register "PcieRpLtrEnable[5]" = "1"
			register "PcieClkSrcUsage[10]" = "5"
			register "PcieClkSrcClkReq[10]" = "10"
		end
		device ref pcie_rp8 on
			# PCIe root port #8 x1, Clock 2 (WLAN)
			register "PcieRpEnable[7]" = "1"
			register "PcieRpLtrEnable[7]" = "1"
			register "PcieClkSrcUsage[2]" = "7"
			register "PcieClkSrcClkReq[2]" = "2"
			register "PcieRpSlotImplemented[7]" = "1"
		end
		device ref pcie_rp9 on
			# PCIe root port #9 x4, Clock 6 (SSD2)
			register "PcieRpEnable[8]" = "1"
			register "PcieRpLtrEnable[8]" = "1"
			register "PcieClkSrcUsage[6]" = "8"
			register "PcieClkSrcClkReq[6]" = "6"
			register "PcieRpSlotImplemented[8]" = "1"
		end
		device ref pch_espi on
			register "gen1_dec" = "0x00040069" # EC PM channel
			register "gen2_dec" = "0x00fc0E01" # AP/EC command
			register "gen3_dec" = "0x00fc0F01" # AP/EC debug
			chip drivers/pc80/tpm
				device pnp 0c31.0 on end
			end
		end
		device ref p2sb on end
		device ref pmc hidden end
		device ref hda on
			register "PchHdaAudioLinkHdaEnable" = "1"
		end
		device ref smbus on
			chip drivers/i2c/tas5825m
				register "id" = "0"
				device i2c 4e on end # (8bit address: 0x9c)
			end
		end
		device ref fast_spi on end
	end
end