chip soc/intel/cannonlake
	register "common_soc_config" = "{
		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
		/* Touchpad */
		.i2c[0] = {
			.speed = I2C_SPEED_FAST,
			.rise_time_ns = 80,
			.fall_time_ns = 110,
		},
	}"

	# Send an extra VR mailbox command for the PS4 exit issue
	register "SendVrMbxCmd" = "2"

# ACPI (soc/intel/cannonlake/acpi.c)
	# Disable s0ix
	register "s0ix_enable" = "0"

	# PM Timer Enabled
	register "PmTimerDisabled" = "0"

	# Disable DPTF
	register "dptf_enable" = "0"

# CPU (soc/intel/cannonlake/cpu.c)
	# Power limit
	register "power_limits_config" = "{
		.tdp_pl1_override = 15,
		.tdp_pl2_override = 25,
	}"

	# Enable "Intel Speed Shift Technology"
	register "speed_shift_enable" = "1"

	# Enable Enhanced Intel SpeedStep
	register "eist_enable" = "1"

# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
	register "SaGv" = "SaGv_Enabled"
	#register "enable_c6dram" = "1"

# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
	# Serial I/O
	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad
		[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // LPSS UART
	}"

	# Misc
	register "AcousticNoiseMitigation" = "1"
	#register "dmipwroptimize" = "1"
	#register "satapwroptimize" = "1"

	# Power
	register "PchPmSlpS3MinAssert" = "3"		# 50ms
	register "PchPmSlpS4MinAssert" = "1"		# 1s
	register "PchPmSlpSusMinAssert" = "2"		# 500ms
	register "PchPmSlpAMinAssert" = "4"		# 2s

	# Thermal
	register "tcc_offset" = "12"

# LPC (soc/intel/cannonlake/lpc.c)
	# LPC configuration from lspci -s 1f.0 -xxx
	# Address 0x84: Decode 0x80 - 0x8F (Port 80)
	register "gen1_dec" = "0x000c0081"
	# Address 0x88: Decode 0x68 - 0x6F (PMC)
	register "gen2_dec" = "0x00040069"
	# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
	register "gen3_dec" = "0x00fc0E01"
	# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
	register "gen4_dec" = "0x00fc0F01"

# PM Util (soc/intel/cannonlake/pmutil.c)
	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
	register "gpe0_dw0" = "PMC_GPP_C"
	register "gpe0_dw1" = "PMC_GPP_D"
	register "gpe0_dw2" = "PMC_GPP_E"

# Actual device tree
	device cpu_cluster 0 on
		device lapic 0 on end
	end

	device domain 0 on
		device pci 00.0 on  end # Host Bridge
		device pci 02.0 on  end # Integrated Graphics Device
		device pci 04.0 on      # SA Thermal device
			register "Device4Enable" = "1"
		end
		device pci 12.0 on  end # Thermal Subsystem
		device pci 12.5 off end # UFS SCS
		device pci 12.6 off end # GSPI #2
		device pci 13.0 off end # Integrated Sensor Hub
		device pci 14.0 on	# USB xHCI
			register "SsicPortEnable" = "0"
			# USB2
			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A port 1
			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"		# Type-C port 2
			register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"		# Type-A port 3
			register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)"		# Camera
			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"		# Bluetooth
			# USB3
			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-A port 1
			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-C port 2
			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"		# Type-A port 3
		end
		device pci 14.1 off end # USB xDCI (OTG)
		chip drivers/intel/wifi # CNVi wifi
			register "wake" = "GPE0_PME_B0"
			device pci 14.3 on end
		end
		device pci 14.5 off end # SDCard
		device pci 15.0 on
			chip drivers/i2c/hid
				register "generic.hid" = ""ELAN040D""
				register "generic.desc" = ""ELAN Touchpad""
				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
				register "generic.probed" = "1"
				register "hid_desc_reg_offset" = "0x01"
				device i2c 15 on end
			end
		end # I2C #0
		device pci 15.1 off end # I2C #1
		device pci 15.2 off end # I2C #2
		device pci 15.3 off end # I2C #3
		device pci 16.0 off end # Management Engine Interface 1
		device pci 16.1 off end # Management Engine Interface 2
		device pci 16.2 off end # Management Engine IDE-R
		device pci 16.3 off end # Management Engine KT Redirection
		device pci 16.4 off end # Management Engine Interface 3
		device pci 16.5 off end # Management Engine Interface 4
		device pci 17.0 on	# SATA
			register "SataMode" = "Sata_AHCI"
			register "SataSalpSupport" = "0"
			# Port 2 (J_SSD2)
			register "SataPortsEnable[1]" = "1"
			register "SataPortsDevSlp[1]" = "1"
			# Port 3 (J_SSD1)
			register "SataPortsEnable[2]" = "1"
			register "SataPortsDevSlp[2]" = "1"
		end
		device pci 19.0 off end # I2C #4
		device pci 19.1 off end # I2C #5
		device pci 19.2 on  end # UART #2
		device pci 1a.0 off end # eMMC
		device pci 1c.0 off end # PCI Express Port 1
		device pci 1c.1 off end # PCI Express Port 2
		device pci 1c.2 off end # PCI Express Port 3
		device pci 1c.3 off end # PCI Express Port 4
		device pci 1c.4 off end # PCI Express Port 5
		device pci 1c.5 on	# PCI Express Port 6
			device pci 00.0 on end # x1 Card reader
			register "PcieRpEnable[5]" = "1"
			register "PcieRpLtrEnable[5]" = "1"
			register "PcieClkSrcUsage[3]" = "5"
			register "PcieClkSrcClkReq[3]" = "3"
			register "PcieRpSlotImplemented[5]" = "1"
		end
		device pci 1c.6 off end # PCI Express Port 7
		device pci 1c.7 on	# PCI Express Port 8
			device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
			register "PcieRpEnable[7]" = "1"
			register "PcieRpLtrEnable[7]" = "1"
			register "PcieClkSrcUsage[2]" = "7"
			register "PcieClkSrcClkReq[2]" = "2"
			register "PcieRpSlotImplemented[7]" = "1"
			chip drivers/intel/wifi
				device pci 00.0 on end
			end
			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
		end
		device pci 1d.0 on	# PCI Express Port 9
			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
			register "PcieRpEnable[8]" = "1"
			register "PcieRpLtrEnable[8]" = "1"
			register "PcieClkSrcUsage[4]" = "8"
			register "PcieClkSrcClkReq[4]" = "4"
			register "PcieRpSlotImplemented[8]" = "1"
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
		end
		device pci 1d.1 off end # PCI Express Port 10
		device pci 1d.2 off end # PCI Express Port 11
		device pci 1d.3 off end # PCI Express Port 12
		device pci 1d.4 on	# PCI Express Port 13
			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
			register "PcieRpEnable[12]" = "1"
			register "PcieRpLtrEnable[12]" = "1"
			register "PcieClkSrcUsage[5]" = "12"
			register "PcieClkSrcClkReq[5]" = "5"
			register "PcieRpSlotImplemented[12]" = "1"
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
		end
		device pci 1d.5 off end # PCI Express Port 14
		device pci 1d.6 off end # PCI Express Port 15
		device pci 1d.7 off end # PCI Express Port 16
		device pci 1e.0 off end # UART #0
		device pci 1e.1 off end # UART #1
		device pci 1e.2 off end # GSPI #0
		device pci 1e.3 off end # GSPI #1
		device pci 1f.0 on	# LPC Interface
			chip drivers/pc80/tpm	# TPM
				device pnp 0c31.0 on  end
			end
		end
		device pci 1f.1 off end # P2SB
		device pci 1f.2 off end # Power Management Controller
		device pci 1f.3 on	# Intel HDA
			register "PchHdaDspEnable" = "0"
			register "PchHdaAudioLinkHda" = "1"
			register "PchHdaAudioLinkDmic0" = "1"
			register "PchHdaAudioLinkDmic1" = "1"
			register "PchHdaAudioLinkSsp0" = "0"
			register "PchHdaAudioLinkSsp1" = "0"
			register "PchHdaAudioLinkSsp2" = "0"
			register "PchHdaAudioLinkSndw1" = "0"
			register "PchHdaAudioLinkSndw2" = "0"
			register "PchHdaAudioLinkSndw3" = "0"
			register "PchHdaAudioLinkSndw4" = "0"
		end
		device pci 1f.4 on  end # SMBus
		device pci 1f.5 on  end	# PCH SPI
		device pci 1f.6 off end # GbE
	end
end