# SPDX-License-Identifier: GPL-2.0-only

chip soc/intel/cannonlake
	device domain 0 on
		subsystemid 0x1558 0x1401 inherit

		device ref xhci		on
			register "usb2_ports" = "{
				[0] = USB2_PORT_MID(OC_SKIP),		/* Type-A port 1 */
				[1] = USB2_PORT_TYPE_C(OC_SKIP),	/* Type-C port 2 */
				[2] = USB2_PORT_MID(OC_SKIP),		/* Type-A port 3 */
				[6] = USB2_PORT_MAX(OC_SKIP),		/* Camera */
				[9] = USB2_PORT_MID(OC_SKIP),		/* Bluetooth */
			}"
			register "usb3_ports" = "{
				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* Type-A port 1 */
				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* Type-C port 2 */
				[2] = USB3_PORT_DEFAULT(OC_SKIP),	/* Type-A port 3 */
			}"
		end
		device ref i2c0		on
			chip drivers/i2c/hid
				register "generic.hid" = ""ELAN040D""
				register "generic.desc" = ""ELAN Touchpad""
				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
				register "generic.detect" = "1"
				register "hid_desc_reg_offset" = "0x01"
				device i2c 15 on end
			end
		end
		device ref sata		on
			register "SataSalpSupport" = "1"
			register "SataPortsEnable" = "{
				[1] = 1, /* Port 2 (J_SSD2) */
				[2] = 1, /* Port 3 (J_SSD1) */
			}"
			register "SataPortsDevSlp" = "{
				[1] = 1, /* Port 2 (J_SSD2) */
				[2] = 1, /* Port 3 (J_SSD1) */
			}"
		end
		device ref pcie_rp6	on
			device pci 00.0 on end # x1 Card reader
			register "PcieRpEnable[5]" = "1"
			register "PcieRpLtrEnable[5]" = "1"
			register "PcieClkSrcUsage[3]" = "5"
			register "PcieClkSrcClkReq[3]" = "3"
			register "PcieRpSlotImplemented[5]" = "1"
		end
		device ref pcie_rp8	on
			device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
			register "PcieRpEnable[7]" = "1"
			register "PcieRpLtrEnable[7]" = "1"
			register "PcieClkSrcUsage[2]" = "7"
			register "PcieClkSrcClkReq[2]" = "2"
			register "PcieRpSlotImplemented[7]" = "1"
			chip drivers/wifi/generic
				device pci 00.0 on end
			end
			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
		end
		device ref pcie_rp9	on
			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
			register "PcieRpEnable[8]" = "1"
			register "PcieRpLtrEnable[8]" = "1"
			register "PcieClkSrcUsage[4]" = "8"
			register "PcieClkSrcClkReq[4]" = "4"
			register "PcieRpSlotImplemented[8]" = "1"
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
		end
		device ref pcie_rp13	on
			device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
			register "PcieRpEnable[12]" = "1"
			register "PcieRpLtrEnable[12]" = "1"
			register "PcieClkSrcUsage[5]" = "12"
			register "PcieClkSrcClkReq[5]" = "5"
			register "PcieRpSlotImplemented[12]" = "1"
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
		end
	end
end