# SPDX-License-Identifier: GPL-2.0-only chip soc/intel/cannonlake register "common_soc_config" = "{ /* Touchpad */ .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 80, .fall_time_ns = 110, }, }" # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 30, }" # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // LPSS UART }" # Misc register "AcousticNoiseMitigation" = "1" # Power register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "1" # 1s register "PchPmSlpSusMinAssert" = "2" # 500ms register "PchPmSlpAMinAssert" = "4" # 2s # Thermal register "tcc_offset" = "12" # Serial IRQ Continuous register "serirq_mode" = "SERIRQ_CONTINUOUS" # PM Util (soc/intel/cannonlake/pmutil.c) # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. register "gpe0_dw0" = "PMC_GPP_C" register "gpe0_dw1" = "PMC_GPP_D" register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree device domain 0 on device ref igpu on register "gfx" = "GMA_DEFAULT_PANEL(0)" end device ref dptf on register "Device4Enable" = "1" end device ref thermal on end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device generic 0 on end end end device ref uart2 on end device ref lpc_espi on register "gen1_dec" = "0x00040069" register "gen2_dec" = "0x00fc0e01" register "gen3_dec" = "0x00fc0f01" chip drivers/pc80/tpm device pnp 0c31.0 on end end end device ref hda on register "PchHdaAudioLinkHda" = "1" end device ref smbus on end end end