# SPDX-License-Identifier: GPL-2.0-only

chip soc/intel/alderlake
	# FIVR configuration
	#   Read EXT_RAIL_CONFIG to determine bitmaps
	#     sudo devmem2 0xfe0011b8
	#     0x0
	#   Read EXT_V1P05_VR_CONFIG
	#     sudo devmem2 0xfe0011c0
	#     0x1a42000
	#   Read EXT_VNN_VR_CONFIG0
	#     sudo devmem2 0xfe0011c4
	#     0x1a42000
	# TODO: v1p05 voltage and vnn icc max?
	register "ext_fivr_settings" = "{
		.configure_ext_fivr = 1,
		.v1p05_enable_bitmap = 0,
		.vnn_enable_bitmap = 0,
		.v1p05_supported_voltage_bitmap = 0,
		.vnn_supported_voltage_bitmap = 0,
		.v1p05_icc_max_ma = 500,
		.vnn_sx_voltage_mv = 1050,
	}"

	# Thermal
	register "tcc_offset" = "10"

	# GPE configuration
	register "pmc_gpe0_dw0" = "PMC_GPP_R"
	register "pmc_gpe0_dw1" = "PMC_GPP_B"
	register "pmc_gpe0_dw2" = "PMC_GPP_D"

	device domain 0 on
		subsystemid 0x1558 0x866d inherit

		device ref pcie5_0 on
			# PCIe PEG2 x8, Clock 3 (DGPU)
			register "cpu_pcie_rp[CPU_RP(2)]" = "{
				.clk_src = 3,
				.clk_req = 3,
				.flags = PCIE_RP_LTR,
			}"
		end
		device ref pcie4_0 on
			# PCIe PEG0 x4, Clock 0 (SSD2)
			register "cpu_pcie_rp[CPU_RP(1)]" = "{
				.clk_src = 0,
				.clk_req = 0,
				.flags = PCIE_RP_LTR,
			}"
		end
		device ref i2c0 on
			# Touchpad I2C bus
			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
			chip drivers/i2c/hid
				register "generic.hid" = ""ELAN0412""
				register "generic.desc" = ""ELAN Touchpad""
				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
				register "generic.detect" = "1"
				register "hid_desc_reg_offset" = "0x01"
				device i2c 15 on end
			end
			chip drivers/i2c/hid
				register "generic.hid" = ""FTCS1000""
				register "generic.desc" = ""FocalTech Touchpad""
				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
				register "generic.detect" = "1"
				register "hid_desc_reg_offset" = "0x01"
				device i2c 38 on end
			end
		end
		device ref i2c1 off end
		device ref tbt_pcie_rp0 off end
		device ref tcss_xhci on
			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
			device ref tcss_root_hub on
				device ref tcss_usb3_port1 on end
			end
		end
		device ref xhci on
			register "usb2_ports" = "{
				[2] = USB2_PORT_TYPE_C(OC_SKIP),	/* J_TYPEC1 */
				[4] = USB2_PORT_MID(OC_SKIP),		/* USB 3.2 Type-A audio board */
				[5] = USB2_PORT_TYPE_C(OC_SKIP),	/* J_TYPEC2 */
				[6] = USB2_PORT_MID(OC_SKIP),		/* Fingerprint */
				[7] = USB2_PORT_MID(OC_SKIP),		/* Camera */
				[8] = USB2_PORT_MID(OC_SKIP),		/* USB 2.0 Type-A audio board */
				[9] = USB2_PORT_MID(OC_SKIP),		/* Bluetooth */
			}"
			register "usb3_ports" = "{
				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* USB 3.2 Type-A audio board */
				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* J_TYPEC2 */
				[2] = USB3_PORT_DEFAULT(OC_SKIP),	/* J_TYPEC1 */
				[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* J_TYPEC1 */
			}"
		end
		device ref pcie_rp5 on
			# PCIe RP#5 x4, Clock 1 (SSD)
			register "pch_pcie_rp[PCH_RP(5)]" = "{
				.clk_src = 1,
				.clk_req = 1,
				.flags = PCIE_RP_LTR,
				.pcie_rp_detect_timeout_ms = 50,
			}"
		end
		device ref pcie_rp9 on
			# PCIe RP#9 x1, Clock 6 (GLAN)
			register "pch_pcie_rp[PCH_RP(9)]" = "{
				.clk_src = 6,
				.clk_req = 6,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end
		device ref pcie_rp10 on
			# PCIe RP#10 x1, Clock 2 (WLAN)
			register "pch_pcie_rp[PCH_RP(10)]" = "{
				.clk_src = 2,
				.clk_req = 2,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end
		device ref pcie_rp11 on
			# PCIe RP#11 x1, Clock 5 (CARD)
			register "pch_pcie_rp[PCH_RP(11)]" = "{
				.clk_src = 5,
				.clk_req = 5,
				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end
	end
end