/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef _GPIO_X11SSH_TF_H
#define _GPIO_X11SSH_TF_H

#include <soc/gpe.h>
#include <soc/gpio.h>

/* Pad configuration was generated automatically using intelp2m utility. */
static const struct pad_config gpio_table[] = {
	/* GPP_A0 - RCIN# */
	/* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A0,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A1 - LAD0 */
	/* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A1,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A2 - LAD1 */
	/* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A2,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A3 - LAD2 */
	/* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A3,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A4 - LAD3 */
	/* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A4,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A5 - LFRAME# */
	/* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A5,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A6 - SERIRQ */
	/* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A6,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A7 - PIRQA# */
	/* PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A7,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A8 - CLKRUN# */
	/* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A8,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A9 - CLKOUT_LPC0 */
	/* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A9,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A10 - CLKOUT_LPC1 */
	/* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A10,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A11 - PME# */
	/* PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A11,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A12 - GPIO */
	/* PAD_CFG_GPO(GPP_A12, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_A12,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_A13 - SUSWARN# */
	/* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A13,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A14 - SUS_STAT# */
	/* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A14,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A15 - SUS_ACK# */
	/* PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A15,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A16 - CLKOUT_48 */
	/* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A16,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A17 - GPIO */
	/* PAD_NC(GPP_A17, NONE), */
	_PAD_CFG_STRUCT(GPP_A17,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_A18 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_A18,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_A19 - RESERVED */

	/* GPP_A20 - GPIO */
	/* PAD_NC(GPP_A20, NONE), */
	_PAD_CFG_STRUCT(GPP_A20,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_A21 - GPIO */
	/* PAD_NC(GPP_A21, NONE), */
	_PAD_CFG_STRUCT(GPP_A21,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_A22 - GPIO */
	/* PAD_NC(GPP_A22, NONE), */
	_PAD_CFG_STRUCT(GPP_A22,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_A23 - GPIO */
	/* PAD_NC(GPP_A23, NONE), */
	_PAD_CFG_STRUCT(GPP_A23,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B0 - GPIO */
	/* PAD_CFG_GPO(GPP_B0, 1, DEEP), */
	_PAD_CFG_STRUCT(GPP_B0,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_B1 - GPIO */
	/* PAD_CFG_GPO(GPP_B1, 1, DEEP), */
	_PAD_CFG_STRUCT(GPP_B1,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_B2 - GPIO */
	/* PAD_NC(GPP_B2, NONE), */
	_PAD_CFG_STRUCT(GPP_B2,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B3 - GPIO */
	/* PAD_NC(GPP_B3, NONE), */
	_PAD_CFG_STRUCT(GPP_B3,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B4 - GPIO */
	/* PAD_NC(GPP_B4, NONE), */
	_PAD_CFG_STRUCT(GPP_B4,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B5 - GPIO */
	/* PAD_NC(GPP_B5, NONE), */
	_PAD_CFG_STRUCT(GPP_B5,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B6 - GPIO */
	/* PAD_NC(GPP_B6, NONE), */
	_PAD_CFG_STRUCT(GPP_B6,
		PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B7 - GPIO */
	/* PAD_NC(GPP_B7, NONE), */
	_PAD_CFG_STRUCT(GPP_B7,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B8 - GPIO */
	/* PAD_NC(GPP_B8, NONE), */
	_PAD_CFG_STRUCT(GPP_B8,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B9 - GPIO */
	/* PAD_NC(GPP_B9, NONE), */
	_PAD_CFG_STRUCT(GPP_B9,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B10 - GPIO */
	/* PAD_NC(GPP_B10, NONE), */
	_PAD_CFG_STRUCT(GPP_B10,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B11 - GPIO */
	/* PAD_CFG_GPO(GPP_B11, 0, DEEP), */
	_PAD_CFG_STRUCT(GPP_B11,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),

	/* GPP_B12 - SLP_S0# */
	/* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_B12,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_B13 - PLTRST# */
	/* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_B13,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_B14 - SPKR */
	/* PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), */
	_PAD_CFG_STRUCT(GPP_B14,
		PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),

	/* GPP_B15 - GPIO */
	/* PAD_NC(GPP_B15, NONE), */
	_PAD_CFG_STRUCT(GPP_B15,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B16 - GPIO */
	/* PAD_NC(GPP_B16, NONE), */
	_PAD_CFG_STRUCT(GPP_B16,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B17 - GPIO */
	/* PAD_NC(GPP_B17, NONE), */
	_PAD_CFG_STRUCT(GPP_B17,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B18 - GPIO */
	/* PAD_NC(GPP_B18, NONE), */
	_PAD_CFG_STRUCT(GPP_B18,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B19 - GPIO */
	/* PAD_NC(GPP_B19, NONE), */
	_PAD_CFG_STRUCT(GPP_B19,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B20 - GPIO */
	/* PAD_CFG_GPO(GPP_B20, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_B20,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_B21 - GPIO */
	/* PAD_NC(GPP_B21, NONE), */
	_PAD_CFG_STRUCT(GPP_B21,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B22 - GPIO */
	/* PAD_NC(GPP_B22, NONE), */
	_PAD_CFG_STRUCT(GPP_B22,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_B23 - PCHHOT# */
	/* PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), */
	_PAD_CFG_STRUCT(GPP_B23,
		PAD_FUNC(NF2) | PAD_RESET(DEEP), 0),

	/* GPP_C0 - RESERVED */

	/* GPP_C1 - RESERVED */

	/* GPP_C2 - GPIO */
	/* PAD_NC(GPP_C2, NONE), */
	_PAD_CFG_STRUCT(GPP_C2,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C3 - RESERVED */

	/* GPP_C4 - RESERVED */

	/* GPP_C5 - GPIO */
	/* PAD_CFG_GPO(GPP_C5, 1, DEEP), */
	_PAD_CFG_STRUCT(GPP_C5,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_C6 - RESERVED */

	/* GPP_C7 - RESERVED */

	/* GPP_C8 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_C8,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_C9 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_C9,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_C10 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_C10,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_C11 - GPIO */
	/* PAD_NC(GPP_C11, NONE), */
	_PAD_CFG_STRUCT(GPP_C11,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C12 - GPIO */
	/* PAD_NC(GPP_C12, NONE), */
	_PAD_CFG_STRUCT(GPP_C12,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C13 - GPIO */
	/* PAD_NC(GPP_C13, NONE), */
	_PAD_CFG_STRUCT(GPP_C13,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C14 - GPIO */
	/* PAD_NC(GPP_C14, NONE), */
	_PAD_CFG_STRUCT(GPP_C14,
		PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C15 - GPIO */
	/* PAD_NC(GPP_C15, NONE), */
	_PAD_CFG_STRUCT(GPP_C15,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C16 - GPIO */
	/* PAD_NC(GPP_C16, NONE), */
	_PAD_CFG_STRUCT(GPP_C16,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C17 - GPIO */
	/* PAD_NC(GPP_C17, NONE), */
	_PAD_CFG_STRUCT(GPP_C17,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C18 - GPIO */
	/* PAD_NC(GPP_C18, NONE), */
	_PAD_CFG_STRUCT(GPP_C18,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C19 - GPIO */
	/* PAD_NC(GPP_C19, NONE), */
	_PAD_CFG_STRUCT(GPP_C19,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C20 - GPIO */
	/* PAD_NC(GPP_C20, NONE), */
	_PAD_CFG_STRUCT(GPP_C20,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C21 - GPIO */
	/* PAD_NC(GPP_C21, NONE), */
	_PAD_CFG_STRUCT(GPP_C21,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_C22 - GPIO */
	/* PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), */
	_PAD_CFG_STRUCT(GPP_C22,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_BUF(TX_DISABLE),
		PAD_PULL(20K_PU)),

	/* GPP_C23 - GPIO */
	/* PAD_NC(GPP_C23, NONE), */
	_PAD_CFG_STRUCT(GPP_C23,
		PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D0 - GPIO */
	/* PAD_NC(GPP_D0, NONE), */
	_PAD_CFG_STRUCT(GPP_D0,
		PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D1 - GPIO */
	/* PAD_CFG_GPO(GPP_D1, 1, DEEP), */
	_PAD_CFG_STRUCT(GPP_D1,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_D2 - GPIO */
	/* PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), */
	_PAD_CFG_STRUCT(GPP_D2,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE),
		PAD_PULL(20K_PU)),

	/* GPP_D3 - GPIO */
	/* PAD_NC(GPP_D3, NONE), */
	_PAD_CFG_STRUCT(GPP_D3,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D4 - GPIO */
	/* PAD_CFG_GPO(GPP_D4, 0, PLTRST), */
	_PAD_CFG_STRUCT(GPP_D4,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),

	/* GPP_D5 - GPIO */
	/* PAD_NC(GPP_D5, NONE), */
	_PAD_CFG_STRUCT(GPP_D5,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D6 - GPIO */
	/* PAD_NC(GPP_D6, NONE), */
	_PAD_CFG_STRUCT(GPP_D6,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D7 - GPIO */
	/* PAD_NC(GPP_D7, NONE), */
	_PAD_CFG_STRUCT(GPP_D7,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D8 - GPIO */
	/* PAD_NC(GPP_D8, NONE), */
	_PAD_CFG_STRUCT(GPP_D8,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D9 - GPIO */
	/* PAD_NC(GPP_D9, NONE), */
	_PAD_CFG_STRUCT(GPP_D9,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D10 - GPIO */
	/* PAD_NC(GPP_D10, NONE), */
	_PAD_CFG_STRUCT(GPP_D10,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D11 - GPIO */
	/* PAD_NC(GPP_D11, NONE), */
	_PAD_CFG_STRUCT(GPP_D11,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D12 - GPIO */
	/* PAD_NC(GPP_D12, NONE), */
	_PAD_CFG_STRUCT(GPP_D12,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D13 - GPIO */
	/* PAD_NC(GPP_D13, NONE), */
	_PAD_CFG_STRUCT(GPP_D13,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D14 - GPIO */
	/* PAD_NC(GPP_D14, NONE), */
	_PAD_CFG_STRUCT(GPP_D14,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D15 - GPIO */
	/* PAD_NC(GPP_D15, NONE), */
	_PAD_CFG_STRUCT(GPP_D15,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D16 - GPIO */
	/* PAD_NC(GPP_D16, NONE), */
	_PAD_CFG_STRUCT(GPP_D16,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D17 - GPIO */
	/* PAD_NC(GPP_D17, NONE), */
	_PAD_CFG_STRUCT(GPP_D17,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D18 - GPIO */
	/* PAD_CFG_GPO(GPP_D18, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_D18,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_D19 - GPIO */
	/* PAD_CFG_GPO(GPP_D19, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_D19,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_D20 - GPIO */
	/* PAD_NC(GPP_D20, NONE), */
	_PAD_CFG_STRUCT(GPP_D20,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_D21 - GPIO */
	/* PAD_CFG_GPO(GPP_D21, 0, DEEP), */
	_PAD_CFG_STRUCT(GPP_D21,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),

	/* GPP_D22 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_D22,
		PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_D23 - GPIO */
	/* PAD_NC(GPP_D23, NONE), */
	_PAD_CFG_STRUCT(GPP_D23,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_E0 - SATAXPCIE0 */
	/* PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_E0,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_E1 - GPIO */
	/* PAD_NC(GPP_E1, NONE), */
	_PAD_CFG_STRUCT(GPP_E1,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_E2 - GPIO */
	/* PAD_NC(GPP_E2, NONE), */
	_PAD_CFG_STRUCT(GPP_E2,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_E3 - GPIO */
	/* PAD_NC(GPP_E3, NONE), */
	_PAD_CFG_STRUCT(GPP_E3,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_E4 - GPIO */
	/* PAD_NC(GPP_E4, NONE), */
	_PAD_CFG_STRUCT(GPP_E4,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_E5 - GPIO */
	/* PAD_NC(GPP_E5, NONE), */
	_PAD_CFG_STRUCT(GPP_E5,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_E6 - GPIO */
	/* PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), */
	_PAD_CFG_STRUCT(GPP_E6,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_DISABLE),
		PAD_PULL(20K_PU)),

	/* GPP_E7 - GPIO */
	/* PAD_NC(GPP_E7, NONE), */
	_PAD_CFG_STRUCT(GPP_E7,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_E8 - SATA_LED# */
	/* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_E8,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_E9 - USB_OC0# */
	/* PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_E9,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_E10 - USB_OC1# */
	/* PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_E10,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_E11 - USB_OC2# */
	/* PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_E11,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_E12 - USB_OC3# */
	/* PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_E12,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_F0 - GPIO */
	/* PAD_NC(GPP_F0, NONE), */
	_PAD_CFG_STRUCT(GPP_F0,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F1 - GPIO */
	/* PAD_NC(GPP_F1, NONE), */
	_PAD_CFG_STRUCT(GPP_F1,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F2 - GPIO */
	/* PAD_NC(GPP_F2, NONE), */
	_PAD_CFG_STRUCT(GPP_F2,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F3 - GPIO */
	/* PAD_NC(GPP_F3, NONE), */
	_PAD_CFG_STRUCT(GPP_F3,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F4 - GPIO */
	/* PAD_NC(GPP_F4, NONE), */
	_PAD_CFG_STRUCT(GPP_F4,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F5 - GPIO */
	/* PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), */
	_PAD_CFG_STRUCT(GPP_F5,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_F6 - GPIO */
	/* PAD_CFG_GPO(GPP_F6, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_F6,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_F7 - GPIO */
	/* PAD_CFG_GPO(GPP_F7, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_F7,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_F8 - GPIO */
	/* PAD_CFG_GPO(GPP_F8, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_F8,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_F9 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_F9,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_F10 - SATA_SCLOCK */
	/* PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_F10,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_F11 - SATA_SLOAD */
	/* PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_F11,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_F12 - SATA_SDATAOUT1 */
	/* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_F12,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_F13 - SATA_SDATAOUT2 */
	/* PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_F13,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_F14 - GPIO */
	/* PAD_NC(GPP_F14, NONE), */
	_PAD_CFG_STRUCT(GPP_F14,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F15 - USB_OC4# */
	/* PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_F15,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_F16 - USB_OC5# */
	/* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_F16,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_F17 - GPIO */
	/* PAD_NC(GPP_F17, NONE), */
	_PAD_CFG_STRUCT(GPP_F17,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F18 - GPIO */
	/* PAD_NC(GPP_F18, NONE), */
	_PAD_CFG_STRUCT(GPP_F18,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F19 - GPIO */
	/* PAD_NC(GPP_F19, NONE), */
	_PAD_CFG_STRUCT(GPP_F19,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F20 - GPIO */
	/* PAD_NC(GPP_F20, NONE), */
	_PAD_CFG_STRUCT(GPP_F20,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F21 - GPIO */
	/* PAD_NC(GPP_F21, NONE), */
	_PAD_CFG_STRUCT(GPP_F21,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F22 - GPIO */
	/* PAD_NC(GPP_F22, NONE), */
	_PAD_CFG_STRUCT(GPP_F22,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_F23 - GPIO */
	/* PAD_CFG_GPO(GPP_F23, 0, RSMRST), */
	_PAD_CFG_STRUCT(GPP_F23,
		PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),

	/* GPP_G0 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_G0,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_G1 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_G1,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_G2 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_G2,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_G3 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_G3,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_G4 - GPIO */
	/* PAD_NC(GPP_G4, NONE), */
	_PAD_CFG_STRUCT(GPP_G4,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G5 - GPIO */
	/* PAD_NC(GPP_G5, NONE), */
	_PAD_CFG_STRUCT(GPP_G5,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G6 - GPIO */
	/* PAD_NC(GPP_G6, NONE), */
	_PAD_CFG_STRUCT(GPP_G6,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G7 - GPIO */
	/* PAD_NC(GPP_G7, NONE), */
	_PAD_CFG_STRUCT(GPP_G7,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G8 - GPIO */
	/* PAD_NC(GPP_G8, NONE), */
	_PAD_CFG_STRUCT(GPP_G8,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G9 - GPIO */
	/* PAD_NC(GPP_G9, NONE), */
	_PAD_CFG_STRUCT(GPP_G9,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G10 - GPIO */
	/* PAD_NC(GPP_G10, NONE), */
	_PAD_CFG_STRUCT(GPP_G10,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G11 - GPIO */
	/* PAD_NC(GPP_G11, NONE), */
	_PAD_CFG_STRUCT(GPP_G11,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G12 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_G12,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_G13 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_G13,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_G14 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_G14,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_G15 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_G15,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_G16 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_G16,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_G17 - GPIO */
	/* PAD_NC(GPP_G17, NONE), */
	_PAD_CFG_STRUCT(GPP_G17,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G18 - NMI# */
	/* PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_G18,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_G19 - SMI# */
	/* PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_G19,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_G20 - GPIO */
	/* PAD_NC(GPP_G20, NONE), */
	_PAD_CFG_STRUCT(GPP_G20,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G21 - GPIO */
	/* PAD_NC(GPP_G21, NONE), */
	_PAD_CFG_STRUCT(GPP_G21,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G22 - GPIO */
	/* PAD_NC(GPP_G22, NONE), */
	_PAD_CFG_STRUCT(GPP_G22,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_G23 - GPIO */
	/* PAD_NC(GPP_G23, NONE), */
	_PAD_CFG_STRUCT(GPP_G23,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_H0 - GPIO */
	/* PAD_CFG_GPO(GPP_H0, 1, DEEP), */
	_PAD_CFG_STRUCT(GPP_H0,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_H1 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_H1,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_H2 - GPIO */
	/* PAD_CFG_GPO(GPP_H2, 1, DEEP), */
	_PAD_CFG_STRUCT(GPP_H2,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_H3 - SRCCLKREQ9# */
	/* PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_H3,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_H4 - GPIO */
	/* PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, PLTRST, OFF, ACPI), */
	_PAD_CFG_STRUCT(GPP_H4,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),

	/* GPP_H5 - GPIO */
	/* PAD_CFG_GPO(GPP_H5, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_H5,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_H6 - GPIO */
	/* PAD_CFG_GPO(GPP_H6, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_H6,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_H7 - GPIO */
	/* PAD_CFG_GPO(GPP_H7, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_H7,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_H8 - GPIO */
	/* PAD_CFG_GPO(GPP_H8, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_H8,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_H9 - GPIO */
	/* PAD_CFG_GPO(GPP_H9, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_H9,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_H10 - SML2CLK */
	/* PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_H10,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_H11 - SML2DATA */
	/* PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_H11,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_H12 - GPIO */
	/* PAD_NC(GPP_H12, NONE), */
	_PAD_CFG_STRUCT(GPP_H12,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_H13 - SML3CLK */
	/* PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_H13,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_H14 - SML3DATA */
	/* PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_H14,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_H15 - GPIO */
	/* PAD_NC(GPP_H15, NONE), */
	_PAD_CFG_STRUCT(GPP_H15,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_H16 - SML4CLK */
	/* PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_H16,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_H17 - SML4DATA */
	/* PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_H17,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_H18 - GPIO */
	/* PAD_NC(GPP_H18, NONE), */
	_PAD_CFG_STRUCT(GPP_H18,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_H19 - GPIO */
	/* PAD_CFG_GPO(GPP_H19, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_H19,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_H20 - GPIO */
	/* PAD_CFG_GPO(GPP_H20, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_H20,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_H21 - GPIO */
	/* PAD_CFG_GPO(GPP_H21, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_H21,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_H22 - GPIO */
	/* PAD_CFG_GPO(GPP_H22, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_H22,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPP_H23 - GPIO */
	/* PAD_CFG_GPO(GPP_H23, 1, PLTRST), */
	_PAD_CFG_STRUCT(GPP_H23,
		PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),

	/* GPD0 - GPIO */
	/* PAD_NC(GPD0, NONE), */
	_PAD_CFG_STRUCT(GPD0,
		PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPD1 - GPIO */
	/* PAD_NC(GPD1, NONE), */
	_PAD_CFG_STRUCT(GPD1,
		PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPD2 - LAN_WAKE# */
	/* PAD_CFG_NF(GPD2, NONE, PWROK, NF1), */
	_PAD_CFG_STRUCT(GPD2,
		PAD_FUNC(NF1), 0),

	/* GPD3 - PWRBTN# */
	/* PAD_CFG_NF(GPD3, NONE, PWROK, NF1), */
	_PAD_CFG_STRUCT(GPD3,
		PAD_FUNC(NF1), 0),

	/* GPD4 - SLP_S3# */
	/* PAD_CFG_NF(GPD4, NONE, PWROK, NF1), */
	_PAD_CFG_STRUCT(GPD4,
		PAD_FUNC(NF1), 0),

	/* GPD5 - SLP_S4# */
	/* PAD_CFG_NF(GPD5, NONE, PWROK, NF1), */
	_PAD_CFG_STRUCT(GPD5,
		PAD_FUNC(NF1), 0),

	/* GPD6 - SLP_A# */
	/* PAD_CFG_NF(GPD6, NONE, PWROK, NF1), */
	_PAD_CFG_STRUCT(GPD6,
		PAD_FUNC(NF1), 0),

	/* GPD7 - GPIO */
	/* PAD_NC(GPD7, NONE), */
	_PAD_CFG_STRUCT(GPD7,
		PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPD8 - SUSCLK */
	/* PAD_CFG_NF(GPD8, NONE, PWROK, NF1), */
	_PAD_CFG_STRUCT(GPD8,
		PAD_FUNC(NF1), 0),

	/* GPD9 - GPIO */
	/* PAD_NC(GPD9, NONE), */
	_PAD_CFG_STRUCT(GPD9,
		PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPD10 - GPIO */
	/* PAD_NC(GPD10, NONE), */
	_PAD_CFG_STRUCT(GPD10,
		PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPD11 - GPIO */
	/* PAD_NC(GPD11, NONE), */
	_PAD_CFG_STRUCT(GPD11,
		PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_I0 - DDPB_HPD0 */
	/* PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_I0,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_I1 - DDPC_HPD1 */
	/* PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_I1,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_I2 - DDPD_HPD2 */
	/* PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_I2,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_I3 - DDPE_HPD3 */
	/* PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), */
	_PAD_CFG_STRUCT(GPP_I3,
		PAD_FUNC(NF1) | PAD_RESET(PLTRST), 0),

	/* GPP_I4 - GPIO */
	/* PAD_NC(GPP_I4, NONE), */
	_PAD_CFG_STRUCT(GPP_I4,
		PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),

	/* GPP_I5 - DDPB_CTRLCLK */
	/* PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_I5,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_I6 - DDPB_CTRLDATA */
	/* PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_I6,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_I7 - DDPC_CTRLCLK */
	/* PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_I7,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_I8 - DDPC_CTRLDATA */
	/* PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_I8,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_I9 - DDPD_CTRLCLK */
	/* PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_I9,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_I10 - DDPD_CTRLDATA */
	/* PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_I10,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
};


/*** XXX TODO XXX */
/* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
	/* LPC */

	/* GPP_A1 - LAD0 */
	/* PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A1,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A2 - LAD1 */
	/* PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A2,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A3 - LAD2 */
	/* PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A3,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A4 - LAD3 */
	/* PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A4,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A5 - LFRAME# */
	/* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A5,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A6 - SERIRQ */
	/* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A6,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A8 - CLKRUN# */
	/* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A8,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A9 - CLKOUT_LPC0 */
	/* PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A9,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),

	/* GPP_A10 - CLKOUT_LPC1 */
	/* PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), */
	_PAD_CFG_STRUCT(GPP_A10,
		PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
};

#endif /* _GPIO_X11SSH_TF_H */