chip soc/intel/cannonlake
	# Enable Enhanced Intel SpeedStep
	register "eist_enable" = "1"

	register "cpu_pl2_4_cfg" = "baseline"

	register "gen1_dec" = "0x00fc0201"
	register "gen2_dec" = "0x007c0a01"
	register "gen3_dec" = "0x000c03e1"
	register "gen4_dec" = "0x001c02e1"

	# GPIO
	register "PchUnlockGpioPads" = "1"
	register "gpe0_dw0" = "0x2"
	register "gpe0_dw1" = "0x3"
	register "gpe0_dw2" = "0xd"

	# FSP configuration
	register "SaGv" = "SaGv_Enabled"
	register "ScsEmmcHs400Enabled" = "1"

	# Enable eDP device
	register "DdiPortEdp" = "1" # Display Port

	# Enable HPD for DDI ports B/C
	register "DdiPortBHpd" = "1" # HDMI
	register "DdiPortCHpd" = "1" # USB Type-C

	# Enable DDC for DDI port B
	register "DdiPortBDdc" = "1" # HDMI

	register "PchHdaAudioLinkHda" = "1"

	# Misc
	register "AcousticNoiseMitigation" = "1"

	# Power
	register "PchPmSlpS3MinAssert"  = "3"	# 50ms
	register "PchPmSlpS4MinAssert"  = "1"	# 1s
	register "PchPmSlpSusMinAssert" = "2"	# 500ms
	register "PchPmSlpAMinAssert"   = "4"	# 2s

	register "tcc_offset" = "20" # TCC of 80C

	# Enable SERIRQ continuous
	register "serirq_mode" = "SERIRQ_CONTINUOUS"

	register "SkipExtGfxScan" = "1"

	register "enable_c6dram" = "1"

	register "SataPortsEnable[0]" = "1"
	register "SataPortsEnable[2]" = "1"

	register "PcieRpEnable[4]" = "1" # LAN1
	register "PcieRpEnable[5]" = "1" # LAN2
	register "PcieRpEnable[6]" = "1" # LAN3
	register "PcieRpEnable[7]" = "1" # LAN4
	register "PcieRpEnable[8]" = "1" # LAN5
	register "PcieRpEnable[9]" = "1" # LAN6
	register "PcieRpEnable[11]" = "1" # M.2 WiFi
	register "PcieRpEnable[12]" = "1" # M.2 NVMe x4

	# Enable Advanced Error Reporting for RP 5-10, 12, 13
	register "PcieRpAdvancedErrorReporting[4]" = "1"
	register "PcieRpAdvancedErrorReporting[5]" = "1"
	register "PcieRpAdvancedErrorReporting[6]" = "1"
	register "PcieRpAdvancedErrorReporting[7]" = "1"
	register "PcieRpAdvancedErrorReporting[8]" = "1"
	register "PcieRpAdvancedErrorReporting[9]" = "1"
	register "PcieRpAdvancedErrorReporting[11]" = "1"
	register "PcieRpAdvancedErrorReporting[12]" = "1"

	# Enable Latency Tolerance Reporting Mechanism RP 5-10, 12, 13
	register "PcieRpLtrEnable[4]" = "1"
	register "PcieRpLtrEnable[5]" = "1"
	register "PcieRpLtrEnable[6]" = "1"
	register "PcieRpLtrEnable[7]" = "1"
	register "PcieRpLtrEnable[8]" = "1"
	register "PcieRpLtrEnable[9]" = "1"
	register "PcieRpLtrEnable[11]" = "1"
	register "PcieRpLtrEnable[12]" = "1"

	register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
	register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
	register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
	register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE"
	register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
	register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"

	# USB related
	register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
					      USB_PORT_WAKE_ENABLE(2) |
					      USB_PORT_WAKE_ENABLE(3) |
					      USB_PORT_WAKE_ENABLE(4) |
					      USB_PORT_WAKE_ENABLE(5) |
					      USB_PORT_WAKE_ENABLE(6) |
					      USB_PORT_WAKE_ENABLE(7) |
					      USB_PORT_WAKE_ENABLE(8) |
					      USB_PORT_WAKE_ENABLE(9)"

	register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
					      USB_PORT_WAKE_ENABLE(2) |
					      USB_PORT_WAKE_ENABLE(3) |
					      USB_PORT_WAKE_ENABLE(4)"

	register "PchUsb2PhySusPgDisable" = "1"

	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"
	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"
	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"
	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"
	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"
	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"		# M2 WiFi
	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"
	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"
	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"		# 4G/LTE
	register "usb2_ports[9]" = "USB2_PORT_EMPTY"

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"
	register "usb3_ports[4]" = "USB3_PORT_EMPTY"
	register "usb3_ports[5]" = "USB3_PORT_EMPTY"

	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
		[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
		[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
		[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
		[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
		[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
		[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
		[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
	}"

	device domain 0 on
		device ref system_agent on  end
		device ref igpu on  end
		device ref dptf on  end
		device ref gna off end
		device ref thermal on  end
		device ref ufs off end
		device ref gspi2 off end
		device ref xhci on  end
		device ref xdci off end
		device ref sdxc off end
		device ref i2c0 off end
		device ref i2c1 off end
		device ref i2c2 off end
		device ref i2c3 off end
		device ref heci1 on  end
		device ref heci2 off end
		device ref csme_ider off end
		device ref csme_ktr off end
		device ref heci3 off end
		device ref heci4 off end
		device ref sata on  end
		device ref i2c4 off end
		device ref i2c5 off end
		device ref uart2 off end
		device ref emmc on  end
		device ref pcie_rp1 off end
		device ref pcie_rp2 off end
		device ref pcie_rp3 off end
		device ref pcie_rp4 off end
		device ref pcie_rp5 on  end # LAN1
		device ref pcie_rp6 on  end # LAN2
		device ref pcie_rp7 on  end # LAN3
		device ref pcie_rp8 on  end # LAN4
		device ref pcie_rp9 on  end # LAN5
		device ref pcie_rp10 on  end # LAN6
		device ref pcie_rp11 off end
		device ref pcie_rp12 on  end
			smbios_slot_desc	"SlotTypeM2Socket1_SD" "SlotLengthOther"
						"M.2/E 2230 (M2_WIFI2)" "SlotDataBusWidth1X"
		device ref pcie_rp13 on      # NVMe
			smbios_slot_desc	"SlotTypeM2Socket3" "SlotLengthOther"
						"M.2/M 2280 (J1)" "SlotDataBusWidth4X"
		end
		device ref pcie_rp14 off end
		device ref pcie_rp15 off end
		device ref pcie_rp16 off end
		device ref uart0 off end
		device ref uart1 off end
		device ref gspi0 off end
		device ref gspi1 off end
		device ref lpc_espi on
			chip superio/ite/it8784e
				register "TMPIN1.mode"    = "THERMAL_RESISTOR"
				register "TMPIN2.mode"    = "THERMAL_MODE_DISABLED"
				register "TMPIN3.mode"    = "THERMAL_PECI"
				register "TMPIN3.offset"  = "0x63"
				register "ec.vin_mask"    = "VIN_ALL"
				register "ec.smbus_24mhz" = "1"
				register "ec.smbus_en"    = "1"
				# FAN1 is CPU fan (connector on board)
				register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
				register "FAN1.smart.tmpin"     = " 3"
				register "FAN1.smart.tmp_off"   = "40"
				register "FAN1.smart.tmp_start" = "60"
				register "FAN1.smart.tmp_full"  = "85"
				register "FAN1.smart.tmp_delta" = " 2"
				register "FAN1.smart.pwm_start" = "20"
				register "FAN1.smart.slope"     = "24"
				register "FAN2.mode"      = "FAN_MODE_OFF"
				register "FAN3.mode"      = "FAN_MODE_OFF"
				device pnp 2e.1 on	# COM 1
					io 0x60 = 0x3f8
					irq 0x70 = 4
				end
				device pnp 2e.2 on end # COM 2
				device pnp 2e.3 off end # Printer Port
				device pnp 2e.4 on	# Environment Controller
					io 0x60 = 0xa40
					io 0x62 = 0xa30
					irq 0x70 = 9
					irq 0xf0 = 0x80 # clear 3VSB status
				end
				device pnp 2e.5 off end	# Keyboard
				device pnp 2e.6 off end	# Mouse
				device pnp 2e.7 off end	# GPIO
				device pnp 2e.a off end	# CIR
			end
			chip drivers/pc80/tpm
				device pnp 0c31.0 on end
			end
		end
		device ref p2sb hidden end
		device ref pmc hidden end
		device ref hda on  end
		device ref smbus on  end
		device ref fast_spi on  end
		device ref gbe off end
	end
end