chip soc/intel/alderlake

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "pmc_gpe0_dw0" = "GPP_B"
	register "pmc_gpe0_dw1" = "GPP_D"
	register "pmc_gpe0_dw2" = "GPP_E"

	# Enable HECI1 interface
	register "HeciEnabled" = "1"

	device domain 0 on
		device ref pcie5 on end
		device ref igpu on end
		device ref dtt on end
		device ref pcie4_0 on end
		device ref pcie4_1 on end
		device ref tbt_pcie_rp0 on end
		device ref tbt_pcie_rp1 on end
		device ref tbt_pcie_rp2 on end
		device ref tbt_pcie_rp3 on end
		device ref crashlog off end
		device ref tcss_xhci on end
		device ref tcss_dma0 on end
		device ref tcss_dma1 on end
		device ref xhci on end
		device ref cnvi_wifi on end
		device ref i2c0 on end
		device ref i2c1 on end
		device ref i2c2 on end
		device ref i2c3 on end
		device ref heci1 on end
		device ref sata on end
		device ref i2c5 on end
		device ref pcie_rp1 on end
		device ref pcie_rp3 on end # W/A to FSP issue
		device ref pcie_rp4 on end # W/A to FSP issue
		device ref pcie_rp5 on end
		device ref pcie_rp6 on end
		device ref pcie_rp8 on end
		device ref pcie_rp9 on end
		device ref pcie_rp11 on end
		device ref uart0 on end
		device ref gspi0 on end
		device ref p2sb on end
		device ref hda on end
		device ref smbus on end
	end
end