chip soc/intel/alderlake
	# FSP configuration

	register "eist_enable" = "1"

	# Sagv Configuration
	register "sagv" = "SaGv_Enabled"
	register "RMT" = "0"
	register "enable_c6dram" = "1"

	register "pmc_gpe0_dw0" = "GPP_J"
	register "pmc_gpe0_dw1" = "GPP_VPGIO"
	register "pmc_gpe0_dw2" = "GPD"

	# USB Configuration
	# TODO: Verify
	register "usb2_ports[0]" = "USB2_PORT_MID(OC2)"
	register "usb2_ports[1]" = "USB2_PORT_MID(OC1)"
	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"
	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"
	register "usb2_ports[6]" = "USB2_PORT_MID(OC7)"
	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[8]" = "USB2_PORT_MID(OC2)"
	register "usb2_ports[9]" = "USB2_PORT_MID(OC7)"
	register "usb2_ports[10]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[11]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[12]" = "USB2_PORT_MID(OC0)"
	register "usb2_ports[13]" = "USB2_PORT_MID(OC6)"

	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"
	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)"
	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)"
	register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)"
	register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)"
	register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)"
	register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC0)"

	# LPC generic I/O ranges
	register "gen1_dec" = "0x00fc0201"
	register "gen2_dec" = "0x003c0a01"
	register "gen3_dec" = "0x000c03f1"
	register "gen4_dec" = "0x000c0081"

	register "sata_salp_support" = "1"

	register "sata_ports_enable" = "{
		[0] = 1,
		[1] = 1,
		[2] = 1,
		[3] = 1,
		[4] = 1,
		[5] = 1,
		[6] = 1,
		[7] = 1,
	}"

	register "sata_ports_dev_slp" = "{
		[0] = 0,
		[1] = 0,
		[2] = 0,
		[3] = 0,
		[4] = 0,
		[5] = 0,
		[6] = 1,
		[7] = 1,
	}"

	# HDMI on port B
	register "ddi_portB_config" = "1"
	register "ddi_ports_config" = "{
		[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
		[DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
		[DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
		[DDI_PORT_2] = DDI_ENABLE_HPD,
		[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
		[DDI_PORT_4] = DDI_ENABLE_HPD,
	}"

	register "hybrid_storage_mode" = "1"
	register "dmi_power_optimize_disable" = "1"

	device domain 0 on
		subsystemid 0x1462 0x7d25 inherit
		device ref pcie5_0 on
			register "cpu_pcie_rp[CPU_RP(2)]" = "{
				.clk_src = 0,
				.clk_req = 0,
				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG,
				.PcieRpL1Substates = L1_SS_L1_2,
				.pcie_rp_aspm = ASPM_L0S_L1,
			}"
			smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong"
					 "PCI_E1" "SlotDataBusWidth16X"
		end
		device ref pcie5_1 off end
		device ref igpu on end
		device ref pcie4_0 on
			register "cpu_pcie_rp[CPU_RP(1)]" = "{
				.clk_src = 9,
				.clk_req = 9,
				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
				.PcieRpL1Substates = L1_SS_L1_2,
				.pcie_rp_aspm = ASPM_L0S_L1,
			}"
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
					 "M2_1" "SlotDataBusWidth4X"
		end
		device ref crashlog off end
		device ref xhci on end
		device ref cnvi_wifi on
			# Enable CNVi BT
			register "cnvi_bt_core" = "true"
			register "cnvi_bt_audio_offload" = "false"
		end
		device ref heci1 on end
		device ref heci2 off end
		device ref ide_r off end
		device ref kt off end
		device ref heci3 off end
		device ref heci4 off end
		device ref sata on end
		device ref pcie_rp1 on
			register "pch_pcie_rp[PCH_RP(1)]" = "{
				.clk_src = 10,
				.clk_req = 10,
				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
				.PcieRpL1Substates = L1_SS_L1_2,
				.pcie_rp_aspm = ASPM_L0S_L1,
			}"
			smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort"
					 "PCI_E2" "SlotDataBusWidth1X"
		end
		device ref pcie_rp2 on
			register "pch_pcie_rp[PCH_RP(2)]" = "{
				.clk_src = 17,
				.clk_req = 17,
				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
				.PcieRpL1Substates = L1_SS_L1_2,
				.pcie_rp_aspm = ASPM_L0S_L1,
			}"
			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
					 "PCI_E4" "SlotDataBusWidth1X"
		end
		device ref pcie_rp3 on
			# i225 Ethernet, Clock PM unsupported, onboard device
			register "pch_pcie_rp[PCH_RP(3)]" = "{
				.clk_src = 12,
				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
				.PcieRpL1Substates = L1_SS_L1_2,
				.pcie_rp_aspm = ASPM_L0S_L1,
			}"
		end
		device ref pcie_rp4 off end

		device ref pcie_rp5 on
			register "pch_pcie_rp[PCH_RP(5)]" = "{
				.clk_src = 15,
				.clk_req = 15,
				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT,
				.PcieRpL1Substates = L1_SS_L1_2,
				.pcie_rp_aspm = ASPM_L0S_L1,
			}"
			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
					 "PCI_E3" "SlotDataBusWidth4X"
		end

		device ref pcie_rp9 on
			register "pch_pcie_rp[PCH_RP(9)]" = "{
				.clk_src = 13,
				.clk_req = 13,
				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
				.PcieRpL1Substates = L1_SS_L1_2,
				.pcie_rp_aspm = ASPM_L0S_L1,
			}"
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
					 "M2_3" "SlotDataBusWidth4X"
		end

		# These are not enabled. The Flex I/O mode is SATA to cover all 8 SATA ports.
		# There is an ASMedia switch on-board to mux the SATA ports 7, 8 and PCIe
		# 9-12, 21-24 to M2_3 and M2_4 slots
		device ref pcie_rp13 off end
		device ref pcie_rp14 off end
		device ref pcie_rp15 off end
		device ref pcie_rp16 off end
		device ref pcie_rp17 off end
		device ref pcie_rp18 off end
		device ref pcie_rp19 off end
		device ref pcie_rp20 off end

		device ref pcie_rp21 on
			register "pch_pcie_rp[PCH_RP(21)]" = "{
				.clk_src = 14,
				.clk_req = 14,
				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
				.PcieRpL1Substates = L1_SS_L1_2,
				.pcie_rp_aspm = ASPM_L0S_L1,
			}"
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
					 "M2_4" "SlotDataBusWidth4X"
		end

		device ref pcie_rp25 on
			register "pch_pcie_rp[PCH_RP(25)]" = "{
				.clk_src = 8,
				.clk_req = 8,
				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
				.PcieRpL1Substates = L1_SS_L1_2,
				.pcie_rp_aspm = ASPM_L0S_L1,
			}"
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
					 "M2_2" "SlotDataBusWidth4X"
		end
		device ref p2sb on end
		device ref hda on
			subsystemid 0x1462 0x9d25
			register "pch_hda_dsp_enable" = "0"
			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
			register "pch_hda_idisp_codec_enable" = "true"
		end
		device ref smbus on end

		chip drivers/crb
			device mmio 0xfed40000 on end
		end
	end
end