##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

## Based on Options.lb from AMD's DB800 mainboard.

uses HAVE_MP_TABLE
uses CONFIG_ROMFS
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses CONFIG_IDE
uses CONFIG_FS_PAYLOAD
uses CONFIG_FS_EXT2
uses AUTOBOOT_DELAY
uses AUTOBOOT_CMDLINE
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESS
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses DEBUG
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses PIRQ_ROUTE

## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 512*1024

###
### Build options
###
default CONFIG_CONSOLE_VGA = 0
default CONFIG_VIDEO_MB = 8
default CONFIG_PCI_ROM_RUN = 0

##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT = 1

##
## no MP table
##
default HAVE_MP_TABLE = 0

##
## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET = 0

## Delay timer options
##
default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1

##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE = 1
default IRQ_SLOT_COUNT = 7
default PIRQ_ROUTE = 1

##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE = 0

###
### coreboot layout values
###

## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 64 * 1024
default FALLBACK_SIZE = 128 * 1024

##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM = 1
default DCACHE_RAM_BASE = 0xc8000
default DCACHE_RAM_SIZE = 0x08000

##
## Use a small 8K stack
##
default STACK_SIZE = 0x2000

##
## Use a small 16K heap
##
default HEAP_SIZE = 0x4000

##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0

default _RAMBASE = 0x00004000

default CONFIG_ROM_PAYLOAD = 1

##
## The default compiler
##
default CROSS_COMPILE = ""
default CC = "$(CROSS_COMPILE)gcc -m32"
default HOSTCC = "gcc"

##
## The Serial Console
##

# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250 = 1

## Select the serial console baud rate
default TTYS0_BAUD = 115200
#default TTYS0_BAUD = 57600
#default TTYS0_BAUD = 38400
#default TTYS0_BAUD = 19200
#default TTYS0_BAUD = 9600
#default TTYS0_BAUD = 4800
#default TTYS0_BAUD = 2400
#default TTYS0_BAUD = 1200

# Select the serial console base port
default TTYS0_BASE = 0x3f8

# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS = 0x3

# Compile extra debugging code
default DEBUG = 1

##
### Select the coreboot loglevel
##
## EMERG      1   system is unusable
## ALERT      2   action must be taken immediately
## CRIT       3   critical conditions
## ERR        4   error conditions
## WARNING    5   warning conditions
## NOTICE     6   normal but significant condition
## INFO       7   informational
## DEBUG      8   debug-level messages
## SPEW       9   Way too many details

## Request this level of debugging output
default  DEFAULT_CONSOLE_LOGLEVEL = 8
## At a maximum only compile in this level of debugging
default  MAXIMUM_CONSOLE_LOGLEVEL = 8

#
# ROMFS
#
#
default CONFIG_ROMFS=0
end