chip northbridge/intel/sandybridge

	# Enable DisplayPort Hotplug with 6ms pulse
	register "gpu_dp_d_hotplug" = "0x06"

	# Enable Panel as LVDS and configure power delays
	register "gpu_panel_port_select" = "0"			# LVDS
	register "gpu_panel_power_cycle_delay" = "6"		# T7: 500ms
	register "gpu_panel_power_up_delay" = "100"		# T1+T2: 10ms
	register "gpu_panel_power_down_delay" = "100"		# T5+T6: 10ms
	register "gpu_panel_power_backlight_on_delay" = "2100"	# T3: 210ms
	register "gpu_panel_power_backlight_off_delay" = "2100"	# T4: 210ms

	device cpu_cluster 0 on
		chip cpu/intel/socket_rPGA989
			device lapic 0 on end
		end
		chip cpu/intel/model_206ax
			# Magic APIC ID to locate this chip
			device lapic 0xACAC off end

			# Coordinate with HW_ALL
			register "pstate_coord_type" = "0xfe"

			register "c1_acpower" = "1"	# ACPI(C1) = MWAIT(C1)
			register "c2_acpower" = "3"	# ACPI(C2) = MWAIT(C3)
			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)

			register "c1_battery" = "1"	# ACPI(C1) = MWAIT(C1)
			register "c2_battery" = "3"	# ACPI(C2) = MWAIT(C3)
			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)
		end
	end

	device domain 0 on
		device pci 00.0 on end # host bridge
		device pci 01.0 off end # PCIe Bridge for discrete graphics
		device pci 02.0 on end # vga controller

		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
			register "pirqa_routing" = "0x8b"
			register "pirqb_routing" = "0x8a"
			register "pirqc_routing" = "0x8b"
			register "pirqd_routing" = "0x8b"
			register "pirqe_routing" = "0x80"
			register "pirqf_routing" = "0x80"
			register "pirqg_routing" = "0x80"
			register "pirqh_routing" = "0x80"

			# GPI routing
			#  0 No effect (default)
			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
			#  2 SCI (if corresponding GPIO_EN bit is also set)
			register "alt_gp_smi_en" = "0x0000"
			register "gpi1_routing" = "2"
			register "gpi8_routing" = "2"

			# Enable SATA ports 0 & 1
			register "sata_port_map" = "0x3"
			# Set max SATA speed to 6.0 Gb/s
			register "sata_interface_speed_support" = "0x3"

			register "gen1_dec" = "0x7c1601"
			register "gen2_dec" = "0x0c15e1"
			register "gen4_dec" = "0x0c06a1"

			# Enable zero-based linear PCIe root port functions
			register "pcie_port_coalesce" = "1"

			device pci 14.0 on end # USB 3.0 Controller
			device pci 16.0 on end # Management Engine Interface 1
			device pci 16.1 off end # Management Engine Interface 2
			device pci 16.2 off end # Management Engine IDE-R
			device pci 16.3 off end # Management Engine KT
			device pci 19.0 on end # Intel Gigabit Ethernet
			device pci 1a.0 on end # USB2 EHCI #2
			device pci 1b.0 on end # High Definition Audio
			device pci 1c.0 on end # PCIe Port #1
			device pci 1c.1 on end # PCIe Port #2
			device pci 1c.2 on end # PCIe Port #3 (expresscard)
			device pci 1c.3 off end # PCIe Port #4
			device pci 1c.4 off end # PCIe Port #5
			device pci 1c.5 off end # PCIe Port #6
			device pci 1c.6 off end # PCIe Port #7
			device pci 1c.7 off end # PCIe Port #8
			device pci 1d.0 on end # USB2 EHCI #1
			device pci 1e.0 off end # PCI bridge
			device pci 1f.0 on #LPC bridge
				chip ec/lenovo/pmh7
					device pnp ff.1 on # dummy
					end
					register "backlight_enable" = "0x01"
					register "dock_event_enable" = "0x01"
				end

				chip ec/lenovo/h8
					device pnp ff.2 on # dummy
						io 0x60 = 0x62
						io 0x62 = 0x66
						io 0x64 = 0x1600
						io 0x66 = 0x1604
					end

					register "config0" = "0xa6"
					register "config1" = "0x09"
					register "config2" = "0xa0"
					register "config3" = "0xe0"

					register "has_keyboard_backlight" = "1"

					register "beepmask0" = "0x00"
					register "beepmask1" = "0x86"
					register "has_power_management_beeps" = "0"
					register "event2_enable" = "0xff"
					register "event3_enable" = "0xff"
					register "event4_enable" = "0xd0"
					register "event5_enable" = "0xfc"
					register "event6_enable" = "0x00"
					register "event7_enable" = "0x01"
					register "event8_enable" = "0x7b"
					register "event9_enable" = "0xff"
					register "eventa_enable" = "0x01"
					register "eventb_enable" = "0x00"
					register "eventc_enable" = "0xff"
					register "eventd_enable" = "0xff"
					register "evente_enable" = "0x0d"
				end
			end # LPC bridge
			device pci 1f.2 on end # SATA Controller 1
			device pci 1f.3 on end # SMBus
			device pci 1f.5 off end # SATA Controller 2
			device pci 1f.6 on end # Thermal
		end
	end
end