chip northbridge/intel/sandybridge

	register "gpu_dp_b_hotplug" = "0x04"
	register "gpu_dp_c_hotplug" = "0x04"
	register "gpu_dp_d_hotplug" = "0x04"
	register "gpu_panel_power_cycle_delay" = "3"
	register "gpu_panel_power_up_delay" = "250"		# T1+T2: 25ms
	register "gpu_panel_power_down_delay" = "250"		# T5+T6: 35ms
	register "gpu_panel_power_backlight_on_delay" = "2500"	# T3: 250ms
	register "gpu_panel_power_backlight_off_delay" = "2500"	# T4: 250ms

	register "gpu_cpu_backlight" = "0x1312"
	register "gpu_pch_backlight" = "0x13121312"

	device domain 0 on
		subsystemid 0x17aa 0x21e8 inherit

		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
			register "usb_port_config" = "{
				{ 1, 1, 0 },
				{ 1, 1, 1 },
				{ 1, 1, 3 },
				{ 1, 0, 3 },
				{ 1, 0, 3 },
				{ 1, 1, 3 },
				{ 0, 0, 3 },
				{ 0, 0, 3 },
				{ 1, 1, 4 },
				{ 1, 1, 5 },
				{ 1, 0, 7 },
				{ 1, 1, 7 },
				{ 1, 1, 7 },
				{ 1, 0, 7 }
			}"
			# Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap)
			register "sata_port_map" = "0x1d"
			# X1 does not have ExpressCard slot
			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"

			device ref pcie_rp1 off end
			device ref pcie_rp3 off end
			device ref pcie_rp4 off end
			device ref lpc on
				chip ec/lenovo/h8
					device pnp ff.2 on end # dummy
					register "config2" = "0xe0"
					register "config3" = "0xc0"

					register "beepmask0" = "0xfe"
					register "beepmask1" = "0x96"

					register "event5_enable" = "0x3c"
					register "evente_enable" = "0x3d"
				end
			end
		end
	end
end