# SPDX-License-Identifier: GPL-2.0-only

chip soc/intel/skylake

	register "PmConfigSlpS3MinAssert"	= "SLP_S3_MIN_ASSERT_50MS"
	register "PmConfigSlpS4MinAssert"	= "SLP_S4_MIN_ASSERT_4S"
	register "PmConfigSlpSusMinAssert"	= "SLP_SUS_MIN_ASSERT_4S"
	register "PmConfigSlpAMinAssert"	= "SLP_A_MIN_ASSERT_2S"
	register "PmConfigPwrCycDur"		= "RESET_POWER_CYCLE_4S"

	# VR Settings Configuration for 2 Domains
	#+----------------+-------+-------+
	#| Domain/Setting | VCC   | VCCGT |
	#+----------------+-------+-------+
	#| Psi1Threshold  | 20A   | 20A   |
	#| Psi2Threshold  | 5A    | 5A    |
	#| Psi3Threshold  | 1A    | 1A    |
	#| Psi3Enable     | 1     | 1     |
	#| Psi4Enable     | 1     | 1     |
	#| ImonSlope      | 0     | 0     |
	#| ImonOffset     | 0     | 0     |
	#| IccMax         | 55A   | 35A   |
	#| VrVoltageLimit | 1.52V | 1.52V |
	#| AcLoadline     | 2.1   | 3.1   |
	#| DcLoadline     | 2.1   | 3.1   |
	#+----------------+-------+-------+
	register "domain_vr_config[VR_IA_CORE]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.icc_max = VR_CFG_AMP(55),
		.voltage_limit = 1520,
		.ac_loadline = 210,
		.dc_loadline = 210,
	}"

	register "domain_vr_config[VR_GT_UNSLICED]" = "{
		.vr_config_enable = 1,
		.psi1threshold = VR_CFG_AMP(20),
		.psi2threshold = VR_CFG_AMP(5),
		.psi3threshold = VR_CFG_AMP(1),
		.psi3enable = 1,
		.psi4enable = 1,
		.imon_slope = 0x0,
		.imon_offset = 0x0,
		.icc_max = VR_CFG_AMP(35),
		.voltage_limit = 1520,
		.ac_loadline = 310,
		.dc_loadline = 310,
	}"

	# Vendor set Psys Pmax to 30W
	register "power_limits_config" = "{
		.psys_pmax = 30,
	}"

	# TODO
	# Send an extra VR mailbox command for the PS4 exit issue
	register "SendVrMbxCmd" = "2"

	device cpu_cluster 0 on end

	device domain 0 on
		device ref igpu		on  end
		device ref gmm		on  end
		device ref south_xhci	on
			register "usb2_ports" = "{
				[0] = USB2_PORT_LONG(OC0),
				[1] = USB2_PORT_LONG(OC0),
				[2] = USB2_PORT_LONG(OC1),
				[3] = USB2_PORT_LONG(OC1),
				[4] = USB2_PORT_LONG(OC2), /* Debug */
			}"
		end
		device ref thermal	on  end
		device ref heci1	on  end
		device ref sata		on
			register "SataSalpSupport" = "1"
			register "SataPortsEnable" = "{
				[0] = 1,
				[1] = 1,
				[2] = 1,
			}"
		end
		device ref pcie_rp9	on
			register "PcieRpEnable[8]" = "1"
		end
		device ref pcie_rp10	on
			register "PcieRpEnable[9]" = "1"
		end
		device ref pcie_rp11	on
			register "PcieRpEnable[10]" = "1"
		end
		device ref lpc_espi	on
			register "serirq_mode" = "SERIRQ_CONTINUOUS"

			# EC/kempld at 0xa80/0xa81
			register "gen1_dec" = "0x00000a81"

			chip drivers/pc80/tpm
				device pnp 0c31.0 on end
			end
			chip ec/kontron/kempld
				register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }"
				device generic 0.0 on end # UART #0
			end
		end
		device ref smbus	on
			chip drivers/i2c/nct7802y
				device i2c 0x2e on end
			end
		end
		device ref fast_spi	on  end
		device ref gbe		on  end
	end
end