##
## This file is part of the coreboot project.
## 
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
## MA 02110-1301 USA
##

##
## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
## 

##
## Only use the option table in a normal image
##
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE

##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
        default ROM_SECTION_SIZE   = FALLBACK_SIZE
        default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
        default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
        default ROM_SECTION_OFFSET = 0
end

##
## Compute the start location and size size of
## The coreboot bootloader.
##
default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)

##
## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=(64*1024)
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )

##
## Set all of the defaults for an x86 architecture
##

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o
driver rtl8168.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end

if HAVE_ACPI_TABLES
	object fadt.o
	object acpi_tables.o
	makerule dsdt.c
		depends "$(MAINBOARD)/dsdt.dsl"
		action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl"
		action  "mv $(PWD)/dsdt.hex dsdt.c"
	end
	object ./dsdt.o
end

object reset.o

if CONFIG_USE_INIT

makerule ./auto.o
	depends "$(MAINBOARD)/auto.c option_table.h"
	action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end

else

makerule ./auto.inc
	depends "$(MAINBOARD)/auto.c option_table.h"
	action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I.  $(CPPFLAGS) $(MAINBOARD)/auto.c -Os -nostdinc -nostdlib -fno-builtin -g -dA -fverbose-asm -Wall -c -S -o $@"
	action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
	action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end

end

##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
if CONFIG_USE_INIT
	ldscript /cpu/x86/32bit/entry32.lds
	ldscript /cpu/x86/car/cache_as_ram.lds
end

##
## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE 
        mainboardinit cpu/x86/16bit/reset16.inc
        ldscript /cpu/x86/16bit/reset16.lds
else
        mainboardinit cpu/x86/32bit/reset32.inc
        ldscript /cpu/x86/32bit/reset32.lds
end


##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds

##
## Setup Cache-As-Ram
##
mainboardinit cpu/intel/model_6ex/cache_as_ram.inc

###
### This is the early phase of coreboot startup 
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
	ldscript /arch/i386/lib/failover.lds
end

###
### O.k. We aren't just an intermediary anymore!
###

if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end

##
## Include the secondary Configuration files 
##
dir /pc80
config chip.h

chip northbridge/intel/i945

        device apic_cluster 0 on
                chip cpu/intel/socket_mFCPGA478
                        device apic 0 on end
                end
        end

        device pci_domain 0 on 
                device pci 00.0 on end # host bridge
		device pci 01.0 off end # i945 PCIe root port
		chip drivers/pci/onboard
			device pci 02.0 on end # vga controller
			# register "rom_address" = "0xfffc0000"	# 256 KB image
			# register "rom_address" = "0xfff80000"	# 512 KB image
			register "rom_address" = "0xfff00000" # 1 MB image
		end
		device pci 02.1 on end # display controller

                chip southbridge/intel/i82801gx
                        register "ide_legacy_combined" = "0x1"
                        register "ide_enable_primary" = "0x1"
                        register "ide_enable_secondary" = "0x1"
                        register "sata_ahci" = "0x0"

                	device pci 1b.0 on end # High Definition Audio
                	device pci 1c.0 on end # PCIe
                	device pci 1c.1 on end # PCIe
                	device pci 1c.2 on end # PCIe
			#device pci 1c.3 off end # PCIe port 4
			#device pci 1c.4 off end # PCIe port 5
			#device pci 1c.5 off end # PCIe port 6
                	device pci 1d.0 on end # USB UHCI
                	device pci 1d.1 on end # USB UHCI
                	device pci 1d.2 on end # USB UHCI
                	device pci 1d.3 on end # USB UHCI
                	device pci 1d.7 on end # USB2 EHCI
                	device pci 1e.0 on end # PCI bridge
			#device pci 1e.2 off end # AC'97 Audio 
			#device pci 1e.3 off end # AC'97 Modem
                        device pci 1f.0 on # LPC bridge
                                chip superio/winbond/w83627thg
					device pnp 2e.0 off		# Floppy
					end
					device pnp 2e.1 off		# Parport
					end
                                        device pnp 2e.2 on
                                                 io 0x60 = 0x3f8
                                                irq 0x70 = 4
                                        end
                                        device pnp 2e.3 on
                                                 io 0x60 = 0x2f8
                                                irq 0x70 = 3
						irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
                                        end
					device pnp 2e.5 on		# Keyboard+Mouse
						 io 0x60 = 0x60
						 io 0x62 = 0x64
						irq 0x70 = 1
						irq 0x72 = 12
						irq 0xf0 = 0x82		# HW accel A20.
					end
					device pnp 2e.7 on		# GPIO1, GAME, MIDI
						 io 0x62 = 0x330
						irq 0x70 = 9
					end
					device pnp 2e.8 on		# GPIO2
						# all default
					end
					device pnp 2e.9 on		# GPIO3/4
						irq 0x30 = 0x03		# does this work?
						irq 0xf0 = 0xfb		# set inputs/outputs
						irq 0xf1 = 0x66
					end
					device pnp 2e.a off		# ACPI
					end
					device pnp 2e.b on		# HWM
						 io 0x60 = 0xa00
						irq 0x70 = 0
					end

                                end
                                chip superio/winbond/w83627thg
                                        device pnp 4e.0 off		# Floppy
					end
					device pnp 4e.1 off		# Parport
					end
                                        device pnp 4e.2 on		# COM3
                                                 io 0x60 = 0x3e8
                                                irq 0x70 = 11
                                        end
                                        device pnp 4e.3 on		# COM4
                                                 io 0x60 = 0x2e8
                                                irq 0x70 = 10
                                        end
					device pnp 4e.5 off		# Keyboard
					end
					device pnp 4e.7 off		# GPIO1, GAME, MIDI
					end
					device pnp 4e.8 off		# GPIO2
					end
					device pnp 4e.9 off		# GPIO3/4
					end
					device pnp 4e.a off		# ACPI
					end
					device pnp 4e.b off		# HWM
					end
                                end

                        end
			#device pci 1f.1 off end # IDE
                        device pci 1f.2 on end  # SATA
                        device pci 1f.3 on end  # SMBus
			#device pci 1f.4 off end # Realtek ID Codec
                end
        end
end