/* * This file is part of the coreboot project. * * Copyright (C) 2007-2010 coresystems GmbH * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include #include #include #include #include #include #include #include #include #include #include #include #include "superio/smsc/sio1007/early_serial.c" #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit.h" #include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/gpio.h" #include #include #include #include "gpio.h" #if CONFIG_CHROMEOS #include #endif static void pch_enable_lpc(void) { device_t dev = PCH_LPC_DEV; int i; /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); /* Enable SuperIO + COM1 + PS/2 Keyboard/Mouse */ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN; pci_write_config16(dev, LPC_EN, lpc_config); /* Map 256 bytes at 0x1600 to the LPC bus. */ pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601); /* Map a range for the runtime registers to the LPC bus. */ pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); for (i = 0; i < ARRAY_SIZE(sio1007_lpc_ports); i++) { if (sio1007_enable_uart_at(sio1007_lpc_ports[i])) { /* Keep COMA UART enable bit on. */ pci_write_config16(dev, LPC_EN, lpc_config | COMA_LPC_EN); break; } } } static void rcba_config(void) { u32 reg32; /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB * D28IP_P4IP ETH0 INTB -> PIRQC * D29IP_E1P EHCI1 INTA -> PIRQD * D26IP_E2P EHCI2 INTA -> PIRQE * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG * D31IP_TTIP THRT INTC -> PIRQH * D27IP_ZIP HDA INTA -> PIRQG (MSI) */ /* Device interrupt pin register (board specific) */ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D30IP) = (NOINT << D30IP_PIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | (INTB << D28IP_P4IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); /* Device interrupt route registers */ DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; RCBA32(FD) = reg32; } // FIXME, this function is generic code that should go to sb/... or // nb/../early_init.c static void early_pch_init(void) { u8 reg8; // reset rtc power status reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); } static void setup_sio_gpios(void) { const u16 port = 0x164e; const u16 runtime_port = 0x180; /* Turn on configuration mode. */ outb(0x55, port); /* Set the GPIO direction, polarity, and type. */ sio1007_setreg(port, 0x31, 1 << 0, 1 << 0); sio1007_setreg(port, 0x32, 0 << 0, 1 << 0); sio1007_setreg(port, 0x33, 0 << 0, 1 << 0); /* Set the base address for the runtime register block. */ sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff); sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff); /* Turn on address decoding for it. */ sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1); /* Set the value of GPIO 10 by changing GP1, bit 0. */ u8 byte; byte = inb(runtime_port + 0xc); byte |= (1 << 0); outb(byte, runtime_port + 0xc); /* Turn off address decoding for it. */ sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1); /* Turn off configuration mode. */ outb(0xaa, port); } void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; u32 pm1_cnt; u16 pm1_sts; #if CONFIG_COLLECT_TIMESTAMPS tsc_t start_romstage_time; tsc_t before_dram_time; tsc_t after_dram_time; tsc_t base_time = { .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) }; #endif struct pei_data pei_data = { pei_version: PEI_VERSION, mchbar: DEFAULT_MCHBAR, dmibar: DEFAULT_DMIBAR, epbar: DEFAULT_EPBAR, pciexbar: CONFIG_MMCONF_BASE_ADDRESS, smbusbar: SMBUS_IO_BASE, wdbbar: 0x4000000, wdbsize: 0x1000, hpet_address: CONFIG_HPET_ADDRESS, rcba: DEFAULT_RCBABASE, pmbase: DEFAULT_PMBASE, gpiobase: DEFAULT_GPIOBASE, thermalbase: 0xfed08000, system_type: 0, // 0 Mobile, 1 Desktop/Server tseg_size: CONFIG_SMM_TSEG_SIZE, spd_addresses: { 0xa0, 0x00, 0xa4, 0x00 }, ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, ec_present: 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel dimm_channel0_disabled: 2, dimm_channel1_disabled: 2, max_ddr3_freq: 1600, usb_port_config: { { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ { 0, 0, 0x0000 }, /* P5: Empty */ { 0, 0, 0x0000 }, /* P6: Empty */ { 0, 0, 0x0000 }, /* P7: Empty */ { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ { 0, 4, 0x0000 }, /* P11: Empty */ { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ }, }; #if CONFIG_COLLECT_TIMESTAMPS start_romstage_time = rdtsc(); #endif if (bist == 0) enable_lapic(); pch_enable_lpc(); /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&emeraldlake2_gpio_map); setup_sio_gpios(); /* Early SuperIO setup */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected\n"); boot_mode = 1; /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); hlt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); /* Check PM1_STS[15] to see if we are waking from Sx */ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); /* Read PM1_CNT[12:10] to determine which Sx state */ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { #if CONFIG_HAVE_ACPI_RESUME printk(BIOS_DEBUG, "Resume from S3 detected.\n"); boot_mode = 2; /* Clear SLP_TYPE. This will break stage2 but * we care for that when we get there. */ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); #else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); #endif } post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); /* Prepare USB controller early in S3 resume */ if (boot_mode == 2) enable_usb_bar(); post_code(0x3a); pei_data.boot_mode = boot_mode; #if CONFIG_COLLECT_TIMESTAMPS before_dram_time = rdtsc(); #endif sdram_initialize(&pei_data); #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = rdtsc(); #endif post_code(0x3b); /* Perform some initialization that must run before stage2 */ early_pch_init(); post_code(0x3c); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); post_code(0x3d); quick_ram_check(); post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; #if CONFIG_EARLY_CBMEM_INIT cbmem_was_initted = !cbmem_initialize(); #else cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() - HIGH_MEMORY_SIZE)); #endif #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ *(u32 *)CBMEM_BOOT_MODE = 0; *(u32 *)CBMEM_RESUME_BACKUP = 0; if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); if (resume_backup_memory) { *(u32 *)CBMEM_BOOT_MODE = boot_mode; *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; } /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); } else if (boot_mode == 2) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); } else { pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } #endif post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); #endif #if CONFIG_COLLECT_TIMESTAMPS timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); #endif #if CONFIG_CONSOLE_CBMEM /* Keep this the last thing this function does. */ cbmemc_reinit(); #endif }