chip northbridge/intel/fsp_sandybridge
	# IGD Displays
	register "gfx.ndid" = "3"
	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"

	# Enable DisplayPort 1 Hotplug with 6ms pulse
	register "gpu_dp_d_hotplug" = "0x06"

	# Enable DisplayPort 0 Hotplug with 6ms pulse
	register "gpu_dp_c_hotplug" = "0x06"

	# Enable DVI Hotplug with 6ms pulse
	register "gpu_dp_b_hotplug" = "0x06"

	device cpu_cluster 0 on
		chip cpu/intel/socket_rPGA989
			device lapic 0 on end
		end
		chip cpu/intel/fsp_model_206ax
			# Magic APIC ID to locate this chip
			device lapic 0xACAC off end

			register "c1_battery" = "3"	# ACPI(C1) = MWAIT(C3)
			register "c2_battery" = "4"	# ACPI(C2) = MWAIT(C6)
			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)

			register "c1_acpower" = "3"	# ACPI(C1) = MWAIT(C3)
			register "c2_acpower" = "4"	# ACPI(C2) = MWAIT(C6)
			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
		end
	end

	device domain 0 on
		device pci 00.0 on end # host bridge
		device pci 02.0 on end # vga controller

		chip southbridge/intel/fsp_bd82x6x # Intel Series 6 Cougar Point PCH
			register "sata_port_map" = "0x3f"

			register "c2_latency" = "1"
			register "p_cnt_throttling_supported" = "0"

			device pci 14.0 on end # XHCI
			device pci 16.0 on end # Management Engine Interface 1
			device pci 16.1 on end # Management Engine Interface 2
			device pci 16.2 off end # Management Engine IDE-R
			device pci 16.3 off end # Management Engine KT
			device pci 19.0 on end # Intel Gigabit Ethernet
			device pci 1a.0 on end # USB2 EHCI #2
			device pci 1b.0 off end # High Definition Audio
			device pci 1c.0 on end # PCIe Port #1
			device pci 1c.1 on end # PCIe Port #2
			device pci 1c.2 on end # PCIe Port #3
			device pci 1c.3 on end # PCIe Port #4
			device pci 1c.4 on end # PCIe Port #5
			device pci 1c.5 on end # PCIe Port #6
			device pci 1c.6 on end # PCIe Port #7
			device pci 1c.7 on end # PCIe Port #8
			device pci 1d.0 on end # USB2 EHCI #1
			device pci 1e.0 off end # PCI bridge
			device pci 1f.0 on # LPC bridge
				# TODO: insert SIO UART and WDT
			end
			device pci 1f.2 on end # SATA Controller 1
			device pci 1f.3 on end # SMBus
			device pci 1f.5 on end # SATA Controller 2
			device pci 1f.6 on end # Thermal
		end
	end
end