chip soc/intel/apollolake

	device cpu_cluster 0 on
		device lapic 0 on end
	end

	register "pcie_rp0_clkreq_pin" = "3"    # wifi/bt
	register "pcie_rp2_clkreq_pin" = "0"    # SSD

	# Integrated Sensor Hub
	register "integrated_sensor_hub_enable" = "0"

	# EMMC TX DATA Delay 1#
	# 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
	# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
	register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required

	# LPSS S0ix Enable
	register "lpss_s0ix_enable" = "1"

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route, i.e., if this route changes then the affected GPE
	# offset bits also need to be changed. This sets the PMC register
	# GPE_CFG fields.
	register "gpe0_dw1" = "PMC_GPE_N_31_0"
	register "gpe0_dw2" = "PMC_GPE_N_63_32"
	register "gpe0_dw3" = "PMC_GPE_SW_31_0"

	device domain 0 on
		device pci 00.0 on end	# - Host Bridge
		device pci 00.1 on end	# - DPTF
		device pci 00.2 on end	# - NPK
		device pci 02.0 on end	# - Gen
		device pci 03.0 on end	# - Iunit
		device pci 0d.0 on end	# - P2SB
		device pci 0d.1 on end	# - PMC
		device pci 0d.2 on end	# - SPI
		device pci 0d.3 on end	# - Shared SRAM
		device pci 0e.0 on end	# - Audio
		device pci 11.0 on end	# - ISH
		device pci 12.0 on end	# - SATA
		device pci 13.0 on end	# - PCIe-A 0
		device pci 13.2 on end	# - Onboard Lan
		device pci 13.3 on end	# - PCIe-A 3
		device pci 14.0 on end	# - PCIe-B 0
		device pci 14.1 on end	# - Onboard M2 Slot(Wifi/BT)
		device pci 15.0 on end	# - XHCI
		device pci 15.1 off end	# - XDCI
		device pci 16.0 on end	# - I2C 0
		device pci 16.1 on end	# - I2C 1
		device pci 16.2 on end	# - I2C 2
		device pci 16.3 on end	# - I2C 3
		device pci 17.0 on end	# - I2C 4
		device pci 17.1 on end	# - I2C 5
		device pci 17.2 on end	# - I2C 6
		device pci 17.3 on end	# - I2C 7
		device pci 18.0 on end	# - UART 0
		device pci 18.1 on end	# - UART 1
		device pci 18.2 on end	# - UART 2
		device pci 18.3 on end	# - UART 3
		device pci 19.0 on end	# - SPI 0
		device pci 19.1 on end	# - SPI 1
		device pci 19.2 on end	# - SPI 2
		device pci 1a.0 on end	# - PWM
		device pci 1b.0 on end	# - SDCARD
		device pci 1c.0 on end	# - eMMC
		device pci 1e.0 off end	# - SDIO
		device pci 1f.0 on	# - LPC
			chip ec/google/chromeec
				device pnp 0c09.0 on end
			end
		end
		device pci 1f.1 on end	# - SMBUS
	end
end