## SPDX-License-Identifier: GPL-2.0-only

chip soc/intel/alderlake
	register "pmc_gpe0_dw0" = "PMC_GPP_A"
	register "pmc_gpe0_dw1" = "PMC_GPP_R"
	register "pmc_gpe0_dw2" = "PMC_GPD"

	register "sagv" = "CONFIG(ODROID_H4_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled"

	register "enable_c6dram" = "true"

	register "tcc_offset" = "10" # TCC of 90C

	device domain 0 on
		device ref igpu on
			register "ddi_portA_config" = "1"
			register "ddi_portB_config" = "1"
			register "ddi_ports_config" = "{
				[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
				[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
				[DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
			}"
		end
		device ref xhci on
			## Yes, the numbering of the three USB2 ports routed to the EXT_HEAD1
			## pin header does not correlate with the numbering of the USB2 ports
			## on the ADL-N SoC. But schematics and lsusb agree with the mapping.
			##
			## For onboard USB Type-A ports, tune PHYs for short trace lengths as
			## the ODROID-H4 is a tiny board (and exact trace length is unknown).
			##
			## The USB2 ports on the EXT_HEAD1 pin header are meant to be cabled.
			## So, have these ports use medium trace length PHY settings instead.

			register "usb2_ports" = "{

#define ODROID_H4_USB2_PORT_REAR { \
	.enable        = 1, \
	.ocpin         = OC_SKIP, \
	.tx_bias       = USB2_BIAS_0MV, \
	.tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
	.pre_emp_bias  = USB2_BIAS_16P9MV, \
	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
}

				[0] = ODROID_H4_USB2_PORT_REAR,		// USB3_LAN1 Bottom
				[1] = ODROID_H4_USB2_PORT_REAR,		// USB3_LAN1 Top
				[2] = USB2_PORT_MID(OC_SKIP),		// EXT_HEAD1 P7
				[3] = USB2_PORT_MID(OC_SKIP),		// EXT_HEAD1 P5
				[4] = ODROID_H4_USB2_PORT_REAR,		// USBLAN1   Top
				[5] = USB2_PORT_MID(OC_SKIP),		// EXT_HEAD1 P6
				[6] = ODROID_H4_USB2_PORT_REAR,		// USBLAN1   Bottom
			}"
			register "usb3_ports" = "{
				[0] = USB3_PORT_DEFAULT(OC_SKIP),	// USB3_LAN1 Bottom
				[1] = USB3_PORT_DEFAULT(OC_SKIP),	// USB3_LAN1 Top
			}"

			chip drivers/usb/acpi
				device ref xhci_root_hub on
					chip drivers/usb/acpi
						register "desc"	= ""USB3 Type-A (Bottom Right)""
						register "type"	= "UPC_TYPE_USB3_A"
						device ref usb2_port1 on end
						device ref usb3_port1 on end
					end
					chip drivers/usb/acpi
						register "desc"	= ""USB3 Type-A (Top Right)""
						register "type"	= "UPC_TYPE_USB3_A"
						device ref usb2_port2 on end
						device ref usb3_port2 on end
					end
					chip drivers/usb/acpi
						register "desc"	= ""USB2 P7 (EXT_HEAD1)""
						register "type"	= "UPC_TYPE_PROPRIETARY"
						device ref usb2_port3 on end
					end
					chip drivers/usb/acpi
						register "desc"	= ""USB2 P5 (EXT_HEAD1)""
						register "type"	= "UPC_TYPE_PROPRIETARY"
						device ref usb2_port4 on end
					end
					chip drivers/usb/acpi
						register "desc"	= ""USB2 Type-A (Top Left)""
						register "type"	= "UPC_TYPE_A"
						device ref usb2_port5 on end
					end
					chip drivers/usb/acpi
						register "desc"	= ""USB2 P6 (EXT_HEAD1)""
						register "type"	= "UPC_TYPE_PROPRIETARY"
						device ref usb2_port6 on end
					end
					chip drivers/usb/acpi
						register "desc"	= ""USB2 Type-A (Bottom Left)""
						register "type"	= "UPC_TYPE_A"
						device ref usb2_port7 on end
					end
				end
			end
		end
		device ref i2c0 on
			register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
			register "common_soc_config.i2c[0]" = "{
				.speed = I2C_SPEED_FAST,
				.rise_time_ns = 80,
				.fall_time_ns = 110,
			}"
		end
		device ref i2c1 on
			register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
			register "common_soc_config.i2c[1]" = "{
				.speed = I2C_SPEED_FAST,
				.rise_time_ns = 80,
				.fall_time_ns = 110,
			}"
		end
		device ref emmc on
			register "emmc_enable_hs400_mode" = "true"
		end
		device ref pcie_rp3 on	# LAN1
			register "pch_pcie_rp[PCH_RP(3)]" = "{
				.clk_src = 1,
				.clk_req = 1,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end
		device ref pcie_rp4 on	# LAN2
			register "pch_pcie_rp[PCH_RP(4)]" = "{
				.clk_src = 2,
				.clk_req = 2,
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end
		device ref pcie_rp7 on	# ASM1064B SATA
			register "pch_pcie_rp[PCH_RP(7)]" = "{
				.clk_src = 3,
				.clk_req = 3,	// Use hardwired CLKREQ# to allow clock gating
				.flags = PCIE_RP_LTR | PCIE_RP_AER,
			}"
		end
		device ref pcie_rp9 on	# M.2 M (x4)
			register "pch_pcie_rp[PCH_RP(9)]" = "{
				.clk_src = 0,
				.clk_req = 0,
				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
			}"
			smbios_slot_desc	"SlotTypeM2Socket3" "SlotLengthOther"
						"M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X"
		end
		device ref pch_espi on
			register "gen1_dec" = "0x00fc0201"
			register "gen2_dec" = "0x007c0a01"
			register "gen3_dec" = "0x000c03e1"
			register "gen4_dec" = "0x001c02e1"

			chip superio/ite/it8613e
				register "ec.vin_mask" = "VIN0 | VIN1 | VIN2 | VIN4 | VIN5"
				# TODO: figure out how to make PECI work
				register "TMPIN1.mode" = "THERMAL_DIODE"
				#register "TMPIN1.mode" = "THERMAL_PECI"
				#register "TMPIN1.offset" = "0x56"
				register "FAN2" = "{
					.mode = FAN_SMART_AUTOMATIC,
					.smart = {
						.tmpin     =  1,
						.tmp_off   = 20,
						.tmp_start = 35,
						.tmp_full  = 70,
						.tmp_delta =  1,
						.pwm_start = 20,
						.slope     =  3,
						.smoothing =  0,
					},
				}"

				device pnp 2e.1 on	# COM 1
					io 0x60 = 0x3f8
					irq 0x70 = 4
					irq 0xf0 = 0x01
				end
				device pnp 2e.4 on	# Environment Controller
					io 0x60 = 0xa30
					io 0x62 = 0xa20
					irq 0x70 = 0x00
					irq 0xf0 = 0x80
					irq 0xfc = 0xa0
				end
				device pnp 2e.5 off end	# Keyboard
				device pnp 2e.6 off end	# Mouse
				device pnp 2e.7 on	# GPIO
					io 0x60 = 0xa10
					io 0x62 = 0xa00
				end
				device pnp 2e.a off end	# CIR
			end
		end
		device ref hda on
			register "pch_hda_dsp_enable"			= "true"
			register "pch_hda_sdi_enable[0]"		= "true"
			register "pch_hda_audio_link_hda_enable"	= "true"
			register "pch_hda_idisp_codec_enable"		= "true"
			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
			register "pch_hda_idisp_link_tmode"		= "HDA_TMODE_8T"
		end
		device ref smbus on end

		chip drivers/crb
			device mmio 0xfed40000 on end
		end
	end
end