chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "panel_cfg" = "{ .up_delay_ms = 200, .down_delay_ms = 500, .cycle_delay_ms = 600, .backlight_on_delay_ms = 1, .backlight_off_delay_ms = 200, .backlight_pwm_hz = 1000, }" # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. register "gpe0_dw0" = "GPP_B" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" # Enable DPTF register "dptf_enable" = "1" # Enable S0ix register "s0ix_enable" = "1" # Disable Command TriState register "CmdTriStateDis" = "1" # FSP Configuration register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | #| Psi2Threshold | 2A | 2A | 2A | 2A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #| AcLoadline | 14.4 | 4.2 | 5.7 | 4.47 | #| DcLoadline | 14.0 | 4.17 | 4.2 | 4.3 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, .ac_loadline = 1440, .dc_loadline = 1400, }" register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, .ac_loadline = 420, .dc_loadline = 417, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, .ac_loadline = 570, .dc_loadline = 420, }" register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .voltage_limit = 1520, .ac_loadline = 447, .dc_loadline = 430, }" # Enable Root port 1. register "PcieRpEnable[0]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" # RP 1 uses uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_SHORT(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-A Port register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # H1 register "usb2_ports[8]" = "USB2_PORT_SHORT(OC_SKIP)" # Camera register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ #| I2C0 | Touchscreen | #| I2C1 | Trackpad | #| I2C5 | Audio | #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, .scl_lcnt = 190, .scl_hcnt = 100, .sda_hold = 36, }, }, .i2c[1] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, .scl_lcnt = 170, .scl_hcnt = 100, .sda_hold = 36, }, .early_init = 1, }, .i2c[5] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, .scl_lcnt = 190, .scl_hcnt = 100, .sda_hold = 36, }, }, .gspi[0] = { .speed_mhz = 1, .early_init = 1, }, .pch_thermal_trip = 75, }" # Touchscreen register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Trackpad register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # Audio register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoDisabled, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoPci, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" # PL2 override 18W for AML-Y register "power_limits_config" = "{ .tdp_pl2_override = 18, .psys_pmax = 45, }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_E15" device cpu_cluster 0 on device lapic 0 on end end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # SA thermal subsystem device pci 05.0 off end # SA IMGU device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" device usb 0.0 on chip drivers/usb/acpi register "desc" = ""USB Type C Port 1"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" device usb 2.0 on end end chip drivers/usb/acpi register "desc" = ""USB Type A Port 1"" register "type" = "UPC_TYPE_A" device usb 2.1 on end end chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C8)" device usb 2.2 on end end chip drivers/usb/acpi register "desc" = ""USB Type C Port 2"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" device usb 2.4 on end end chip drivers/usb/acpi register "desc" = ""Camera"" register "type" = "UPC_TYPE_INTERNAL" device usb 2.8 on end end end end end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 14.3 off end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""SISC Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" register "generic.enable_delay_ms" = "105" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x0" device i2c 5c on end end end # I2C #0 device pci 15.1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" # GPP_B5 device i2c 15 on end end end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 device pci 19.1 on chip drivers/i2c/max98927 register "interleave_mode" = "1" register "vmon_slot_no" = "4" register "imon_slot_no" = "5" register "uid" = "0" register "desc" = ""SSM4567 Right Speaker Amp"" register "name" = ""MAXR"" device i2c 39 on end end chip drivers/i2c/max98927 register "interleave_mode" = "1" register "vmon_slot_no" = "6" register "imon_slot_no" = "7" register "uid" = "1" register "desc" = ""SSM4567 Left Speaker Amp"" register "name" = ""MAXL"" device i2c 3A on end end chip drivers/i2c/da7219 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" register "btn_cfg" = "50" register "mic_det_thr" = "500" register "jack_ins_deb" = "20" register "jack_det_rate" = ""32ms_64ms"" register "jack_rem_deb" = "1" register "a_d_btn_thr" = "0xa" register "d_b_btn_thr" = "0x16" register "b_c_btn_thr" = "0x21" register "c_mic_btn_thr" = "0x3e" register "btn_avg" = "4" register "adc_1bit_rpt" = "1" register "micbias_lvl" = "2600" register "mic_amp_in_sel" = ""diff"" device i2c 1A on end end end # I2C #5 device pci 19.2 off end # I2C #4 device pci 1c.0 on chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" # GPP_B0 device pci 00.0 on end end end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" device spi 0 on end end end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 on end # SDCard device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end end end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE end end