chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. register "gpe0_dw0" = "GPP_B" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" # Enable DPTF register "dptf_enable" = "1" # Enable S0ix register "s0ix_enable" = true # FSP Configuration register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | #| Psi2Threshold | 2A | 2A | 2A | 2A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | #| IccMax | 5A | 24A | 24A | 24A | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 | #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(5), .voltage_limit = 1520, .ac_loadline = 1500, .dc_loadline = 1430, }" register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, .ac_loadline = 570, .dc_loadline = 483, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, .ac_loadline = 550, .dc_loadline = 420, }" register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, .ac_loadline = 550, .dc_loadline = 420, }" # Enable Root port 1. register "PcieRpEnable[0]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" # RP 1, Enable Advanced Error Reporting register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" # RP 1 uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ #| I2C0 | Touchscreen | #| I2C1 | H1 | #| I2C2 | Camera | #| I2C3 | Pen | #| I2C4 | Camera | #| I2C5 | Audio | #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, .scl_lcnt = 185, .scl_hcnt = 90, .sda_hold = 36, }, }, .i2c[1] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, .scl_lcnt = 190, .scl_hcnt = 100, .sda_hold = 36, }, .early_init = 1, }, .i2c[2] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, .scl_lcnt = 190, .scl_hcnt = 97, .sda_hold = 36, }, }, .i2c[4] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, .scl_lcnt = 190, .scl_hcnt = 97, .sda_hold = 36, }, }, .i2c[5] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, .scl_lcnt = 190, .scl_hcnt = 98, .sda_hold = 36, }, }, .pch_thermal_trip = 75, }" # Touchscreen register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # H1 register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # Camera register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Pen register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Camera register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Audio register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoDisabled, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" # PL2 override 15W for KBL-Y register "power_limits_config" = "{ .tdp_pl2_override = 15, .psys_pmax = 45, }" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_E15" device cpu_cluster 0 on end device domain 0 on device ref system_agent on end device ref igpu on end device ref sa_thermal on end device ref imgu on end device ref south_xhci on end device ref south_xdci on end device ref thermal on end device ref cio on end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" device i2c 10 on end end chip drivers/i2c/generic register "hid" = ""ATML0001"" register "desc" = ""Atmel Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "detect" = "1" register "has_power_resource" = "1" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" register "enable_delay_ms" = "250" device i2c 4b on end end end device ref i2c1 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" device i2c 50 on end end end device ref i2c2 on end device ref i2c3 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" register "generic.wake" = "GPE0_DW1_12" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end end chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D8)" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" register "key.label" = ""pen_eject"" register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" device generic 0 on end end end device ref heci1 on end device ref heci2 off end device ref csme_ider off end device ref csme_ktr off end device ref heci3 off end device ref sata off end device ref uart2 on end device ref i2c5 on chip drivers/i2c/max98927 register "interleave_mode" = "1" register "vmon_slot_no" = "4" register "imon_slot_no" = "5" register "uid" = "0" register "desc" = ""SSM4567 Right Speaker Amp"" register "name" = ""MAXR"" device i2c 39 on end end chip drivers/i2c/max98927 register "interleave_mode" = "1" register "vmon_slot_no" = "6" register "imon_slot_no" = "7" register "uid" = "1" register "desc" = ""SSM4567 Left Speaker Amp"" register "name" = ""MAXL"" device i2c 3A on end end chip drivers/i2c/generic register "hid" = ""10EC5663"" register "name" = ""RT53"" register "desc" = ""Realtek RT5663"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" register "probed" = "1" device i2c 13 on end end end device ref i2c4 on end device ref pcie_rp1 on chip drivers/wifi/generic register "wake" = "GPE0_DW0_00" device pci 00.0 on end end end device ref pcie_rp2 off end device ref pcie_rp3 off end device ref pcie_rp4 off end device ref pcie_rp5 off end device ref pcie_rp6 off end device ref pcie_rp7 off end device ref pcie_rp8 off end device ref pcie_rp9 off end device ref pcie_rp10 off end device ref pcie_rp11 off end device ref pcie_rp12 off end device ref uart0 on end device ref uart1 off end device ref gspi0 off end device ref gspi1 off end device ref emmc on end device ref sdio off end device ref sdxc on end device ref lpc_espi on chip ec/google/chromeec device pnp 0c09.0 on end end end device ref p2sb on end device ref pmc on end device ref hda on end device ref smbus on end device ref fast_spi on end device ref gbe off end end end