/* * This file is part of the coreboot project. * * Copyright (C) 2007-2010 coresystems GmbH * Copyright (C) 2011 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "ec/google/chromeec/ec.h" #include #include #include #include #include "gpio.h" #include #include #include static void pch_enable_lpc(void) { const struct device *lpc; const struct southbridge_intel_bd82x6x_config *config = NULL; lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); if (!lpc) return; if (lpc->chip_info) config = lpc->chip_info; if (!config) return; /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \ GAMEL_LPC_EN | COMA_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); } static void rcba_config(void) { u32 reg32; southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; RCBA32(FD) = reg32; } static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {41, 42, 43, 10, -1}; char *spd_file; size_t spd_file_len; int spd_index = get_gpios(gpio_vector); printk(BIOS_DEBUG, "spd index %d\n", spd_index); spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_file_len); if (!spd_file) die("SPD data not found."); if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); spd_index = 0; } if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } #include void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBABASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, .ddr3lv_support = 1, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ { 0, 3, 0x0000 }, /* P0: Empty */ { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */ { 0, 3, 0x0000 }, /* P4: Empty */ { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */ { 0, 3, 0x0000 }, /* P6: Empty */ { 0, 3, 0x0000 }, /* P7: Empty */ /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ { 1, 4, 0x0040 }, /* P8: Camera (no OC) */ { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */ { 0, 4, 0x0000 }, /* P10: Empty */ { 0, 4, 0x0000 }, /* P11: Empty */ { 0, 4, 0x0000 }, /* P12: Empty */ { 0, 4, 0x0000 }, /* P13: Empty */ }, }; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); pch_enable_lpc(); /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&link_gpio_map); /* Initialize console device(s) */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected\n"); boot_mode = 1; /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); boot_mode = southbridge_detect_s3_resume() ? 2 : 0; if (boot_mode == 0) { /* This is the fastest way to let users know * the Intel CPU is now alive. */ google_chromeec_kbbacklight(100); } post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); /* Prepare USB controller early in S3 resume */ if (boot_mode == 2) enable_usb_bar(); post_code(0x39); copy_spd(&pei_data); post_code(0x3a); pei_data.boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); rcba_config(); post_code(0x3d); quick_ram_check(); post_code(0x3e); cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); if (CONFIG_LPC_TPM) { init_tpm(boot_mode == 2); } }