#
# This file is part of the coreboot project.
#
# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
chip soc/amd/stoneyridge
	register "spd_addr_lookup" = "
	{
		{ {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0
	}"
	register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
	register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
	register "uma_size" = "128 * MiB"

	device cpu_cluster 0 on
		device lapic 10 on end
	end
	device domain 0 on
		subsystemid 0x1022 0x1410 inherit
		device pci 0.0 on  end # Root Complex
		device pci 1.0 on  end # Internal Graphics P2P bridge 0x98e4
		device pci 1.1 on  end # Internal Multimedia
		device pci 2.0 on  end # PCIe Host Bridge
		device pci 2.1 on  end #
		device pci 2.2 on  end #
		device pci 2.3 on  end #
		device pci 2.4 on  end #
		device pci 2.5 on  end #
		device pci 8.0 on  end # PSP
		device pci 9.0 on  end # PCIe Host Bridge
		device pci 9.2 on  end # HDA
		device pci 10.0 on  end # xHCI
		device pci 11.0 on  end # SATA
		device pci 12.0 on  end # EHCI
		device pci 14.0 on      # SMbus
		end # SMbus
		device pci 14.3 on
		end # LPC
		device pci 14.7 on  end # SD
		device pci 18.0 on  end
		device pci 18.1 on  end
		device pci 18.2 on  end
		device pci 18.3 on  end
		device pci 18.4 on  end
		device pci 18.5 on  end
	end #domain
end	#chip soc/amd/stoneyridge